Manufacturing Bits: June 25


Panel-level consortium Fraunhofer is moving forward with the next phase of its consortium to develop technologies for panel-level packaging. In 2016, Fraunhofer launched the original effort, dubbed the Panel Level Packaging Consortium. The consortium, which had 17 partners, developed various equipment and materials in the arena. Several test layouts were designed for process development on ... » read more

System Bits: June 25


Supercomputers around the world At last week’s International Supercomputing Conference in Frankfurt, Germany, the 53rd biannual list of the Top500 of the most powerful computing systems in the world was released. Broken out by countries of installation, China has 219 of the world’s 500 fastest supercomputers, compared with 116 in the United States. Ranking by percent of list flops, the ... » read more

Power/Performance Bits: June 25


Improving IGBTs Researchers at the University of Tokyo developed a power switching device that surpasses previous performance limits, showing that there may still be gains ahead for the silicon-based devices, which have been thought to be approaching their limits. The team's improved insulated gate bipolar transistor (IGBT) used a scaling approach, and simulations showed that downscaling pa... » read more

Who’s Responsible For Security Breaches?


Semiconductor Engineering sat down to discuss industry attitudes towards safety and security with Dave Kelf, chief marketing officer for Breker Verification; Jacob Wiltgen, solutions architect for functional safety at Mentor, a Siemens Business; David Landoll, solutions architect for OneSpin Solutions; Dennis Ciplickas, vice president of characterization solutions at PDF Solutions; Andrew Dauma... » read more

5nm Vs. 3nm


Foundry vendors are readying the next wave of advanced processes, but their customers will face a myriad of confusing options—including whether to develop chips at 5nm, wait until 3nm, or opt for something in between. The path to 5nm is well-defined compared with 3nm. After that, the landscape becomes more convoluted because foundries are adding half-node processes to the mix, such as 6nm ... » read more

Enabling Practical Processing in and near Memory for Data-Intensive Computing


Source: ETH Zurich and Carnegie Mellon University Talk at DAC 2019. Technical Paper link » read more

Copy-Row DRAM (CROW) : Substrate for Improving DRAM


Source/Credit: ETH Zurich & Carnegie Mellon University Click here for the technical paper and here for the power point slides » read more

U.S. Senate Report On The Equifax Breach


Source: U.S. Senate, Permanent Subcommittee On Investigations Committee on Homeland Security and Governmental Affairs Here's the link to the U.S. Senate report on the Equifax breach » read more

Telle Whitney Receives IEEE Honorary Membership


On May 17 Telle Whitney received the 2019 IEEE Honorary Membership at the 2019 IEEE Vision, Innovation, and Challenges Summit (IEEE VIC Summit) in San Diego for leadership in supporting and promoting women in technology, and for building a highly impactful global organization dedicated to this purpose. Sponsored by IEEE, the grade of Honorary Member is a significant honor bestowed by IEEE a... » read more

Week In Review: Manufacturing, Test


Trade wars In recent testimony before a U.S. government panel considering tariffs on $300 billion worth of Chinese goods, SEMI called for the removal of about 30 tariff lines. These items are central to the semiconductor manufacturing process. “SEMI asserts that these tariffs will harm not only companies operating in the U.S., but other companies as well in the semiconductor supply chain... » read more

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