Research Bits: Sept. 8


Gallium oxide pn diodes Researchers at Nagoya University fabricated functional gallium oxide pn diodes that can carry twice as much electrical current as previous gallium oxide diodes and waste less energy than silicon-based diodes. The key challenge in making the pn diode was creating a stable p-type gallium oxide layer. While gallium oxide's crystal structure easily accepts the atoms need... » read more

IBM Power Processor, This One Goes to 11


Hot Chips 25 was held August 24-26 on the Stanford University campus again this year, with many exciting and interesting presentations. I’ve noticed an overall trend with more focus being placed on overall systems rather than the socket. As the conference name suggests, there’s a history of showcasing chips, but with the increased emphasis on AI and related large-scale computing, efficiency... » read more

Chip Industry Technical Paper Roundup: Sept 8


New technical papers recently added to Semiconductor Engineering’s library: [table id=471 /] Find more semiconductor research papers here. » read more

A Fundamental Rethinking Of Memory Hierarchy Design (Stanford University)


A new technical paper titled "The Future of Memory: Limits and Opportunities" was published by researchers at Stanford University and an independent researcher. Abstract "Memory latency, bandwidth, capacity, and energy increasingly limit performance. In this paper, we reconsider proposed system architectures that consist of huge (many-terabyte to petabyte scale) memories shared among large ... » read more

HW Security: 2.5D and 3D Technologies Provide Opportunities in Designing Secure Systems (UCSB, Columbia)


A new technical paper titled "Leveraging 3D Technologies for Hardware Security: Opportunities and Challenges" was published by researchers at the University of California, Santa Barbara and Columbia University. Abstract "3D die stacking and 2.5D interposer design are promising technologies to improve integration density, performance and cost. Current approaches face serious issues in dealin... » read more

Overview of Incorporating LLMs into EDA, With 3 Case Studies (TU Munich et al.)


A new technical paper titled "Large Language Models (LLMs) for Electronic Design Automation (EDA)" was published by researchers at the Technical University of Munich, University of Stuttgart, New York University, and University of Siegen. Abstract "With the growing complexity of modern integrated circuits, hardware engineers are required to devote more effort to the full design-to-manufactu... » read more

Using AI For Fault Detection And Classification In Manufacturing


Third in a seven-part series: Classic fault detection and classification has some classic problems. It's reactive, time-consuming to set up, and any product change involves significant man-hours. Even then, it still misses a lot of problems, which result in scrap. This is where machine learning can excel, because it can sift through huge amounts of data from thousands of sensors and find outlie... » read more

Chip Industry Week in Review


Cadence plans to buy Hexagon AB's design and engineering business to accelerate expansion in physical AI and system design and analysis. Cadence will pay ~US$3.1 billion in cash and issue stock, with the deal expected to close in early 2026. PWC issued a 104-page in-depth analysis of semiconductor technology and markets, highlighting a broad swath of changes: $1T in annual revenue by 2030, ... » read more

Simulating HW with C Speed and RTL Accuracy for HLS Designs (Georgia Tech)


A new technical paper titled "OmniSim: Simulating Hardware with C Speed and RTL Accuracy for High-Level Synthesis Designs" was published by researchers at Georgia Institute of Technology. Abstract "High-Level Synthesis (HLS) is increasingly popular for hardware design using C/C++ instead of Register-Transfer Level (RTL). To express concurrent hardware behavior in a sequential language like ... » read more

Heterogeneous Multi-Core Architecture Optimizing Power Consumption (TU Dresden)


A new technical paper titled "Balancing Power and Performance With Task Dependencies in Multi-Core Systems" was published by researchers at TU Dresden. Abstract "The increasing use of FPGAs necessitates energy-efficient solutions, particularly for battery-powered applications. Although power dissipation is often perceived as a hardware issue, it can be mitigated through power-saving techniq... » read more

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