Case Study: Production Yield And Throughput Improvement Using The Known Good Socket Analysis
By Jesse Ko - 09 Sep, 2025 - Comments: 0

The test sockets, which are crucial components that directly interface with semiconductor IC packages, have a profound impact on device testing performance. Pins with high CRES not only cause false failures in the test but also lower bin grading results, which in turn increase the manufacturing cost due to reduced production performance. The ever-increasing demand driven by high-performance com... » read more

Lessons From 30 Years In The Trenches On The Future Of Semiconductor Manufacturing
By John Kibarian - 09 Sep, 2025 - Comments: 1

The semiconductor industry has always been a story of constant evolution, titans rising and falling, technologies advancing at breakneck speed, and billions of dollars riding on the difference between first and second place. And today, AI, geopolitics and the increased need for collaboration are reshaping the chip industry once again. After more than three decades navigating the complexities... » read more

Making The Most of Test Resources
By Laura Peters - 09 Sep, 2025 - Comments: 0

Semiconductor testing is undergoing multiple paradigm changes at once with the common goals of producing more known good die per month with low test cost. Achieving these goals requires a delicate balance between yield, quality, and test times. There are multiple ways to go about making better use of existing resources, many of which involve an increasing use of design for test (DFT) methods... » read more

The Hidden Cost Of Contact Resistance
By Gregory Haley - 09 Sep, 2025 - Comments: 1

Contact resistance, or CRES, is one of those problems that most engineers prefer not to think about until it's staring them in the face. For years, it could be managed quietly with routine probe card cleaning or a scheduled socket swap. That approach worked well enough when pin counts were lower and devices pulled less current, but the ground has shifted since then. Today’s AI processors m... » read more

Data Feed Forward And How It Works: Part 2
By Roberto Colecchia - 09 Sep, 2025 - Comments: 0

As chiplets and advanced packaging redefine semiconductor architecture, managing complexity isn’t just about the silicon—it’s about the data. Modern multi-die packages often contain components from different vendors, integrated in 2.5D or 3D configurations. Each die brings its own risks, and diagnosing issues after assembly is increasingly difficult—especially when data isn’t share... » read more

Monitor, Test, And Repair For Multi-Die Health And Reliability
By Yervant Zorian - 09 Sep, 2025 - Comments: 0

Ever since the earliest semiconductor devices, silicon health has been a concern. Systems manufacturers wanted to be sure that their chips worked properly before being soldered onto printed circuit boards (PCBs). They put pressure on semiconductor suppliers to test wafers, individual dies, and assembled parts before they were shipped. A wide range of design-for-test (DFT) approaches were develo... » read more

Infusing Trust Into The Supply Chain
By Anne Meixner - 09 Sep, 2025 - Comments: 0

An expanding supply chain of dies feeding multi-die products is prompting chipmakers to reassess and expand on ways to instill trust from end to end. This reaches deeper than just connecting disparate data. It requires integrating complex systems across vendors and protecting vendor data while instilling confidence in their customers and partners. Yet despite the time and effort that has bee... » read more

Same Chip, Two Destinies: How Power Profiles Improve With On-Chip Monitoring
By Eyal Fayneh - 09 Sep, 2025 - Comments: 0

What happens to critical power-related considerations when the same chip is handled two different ways, with or without visibility from within? This article begins by examining how the absence of on-chip monitoring impacts peak power, average power, and Di/Dt noise (rate of current change), as illustrated in the diagram below and the subsequent discussion. It then details how these aspects c... » read more

The Evolution of DRAM
By Ed Sperling - 08 Sep, 2025 - Comments: 1

DRAM has been around since 1966, but today it's still the same basic 1T 1C bit cell architecture. Yet changes are coming as DRAM is called upon to store and retrieve more data faster. Steve Woo, distinguished inventor and fellow at Rambus, talks about how DRAM works, why there are different flavors, the impact of cooling new solutions in denser configurations, and ongoing issues involving the s... » read more

What Do LLMs Want from Hardware
By Geoff Tate - 08 Sep, 2025 - Comments: 0

Figure 1: Noam Shazeer, Google Gemini vice president, presented this in his Hot Chips 2025 talk. Noam Shazeer is Google’s vice president of engineering for Gemini, their LLM competitor to ChatGPT. He talked recently at Hot Chips: “Predictions for the Next Phase of AI." He has worked on LLMs for a decade since inventing the transformer model in 2017. As his slide says, LLMs can take adv... » read more

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