UEC-LLR: The Future Of Loss Recovery In Ethernet For AI And HPC


As Artificial Intelligence (AI) and High-Performance Computing (HPC) systems become the backbone of modern data centers, they generate and consume a massive amount of data. Traditional Ethernet was not built for such high-bandwidth traffic. In HPCs and AI models, computations are distributed across the nodes and the data is shared in real time with low latency and lossless communication. As ... » read more

For Chip Developers, HW/SW Co-Design Key To Data Center Efficiency


Data centers and high-performance computing (HPC) are the primary enablers of today’s power-hungry AI-driven technology, but chip designers, EDA vendors, and the data centers themselves have a long list of options available to them to help curb AI's power consumption. Chip designers play a critical role in ensuring energy efficient processing from the bottom up, whether that is hardware-so... » read more

System Integration With Standards-Based Automation


Today’s semiconductor designs support a broad range of applications, from mobile and edge devices to AI accelerators and data center systems. To keep pace, design teams are shifting from monolithic systems-on-chip (SoCs) to increasingly complex multi-die and chiplet-based architectures. These heterogeneous systems often incorporate IP developed at different times, by different teams, or sourc... » read more

What Is The Next Generation In RF Circuit Simulation And Optimization?


Throughout a modern radio frequency integrated circuit (RFIC) design and fabrication process, engineers run many types of simulations to verify and validate their decisions, including: electronic circuit simulations RF circuit simulations electromagnetic (EM) simulations thermal simulations and electro-thermal co-simulations post-layout mixed signal (analog and digital) simulat... » read more

Multi-Modal AI In EDA Development Flows


RTL coding is a critical step in the development of semiconductors, but many would argue it is not the most difficult. Things become a lot more complex as you get closer to implementation, and as the system context becomes larger than can be comprehended by text alone. In both cases, layout, timing, power, and many other factors come into play, but none is as easily represented by text, and the... » read more

STA Strategies For Fast And Efficient Signoff Performance For Multi-Billion Instance Designs


Contemporary AI, high-performance computing (HPC), mobile, and automotive designs continue to grow in size and complexity, putting a strain on the high-capacity compute required for static timing analysis (STA) workloads. Designs continue to grow at an unprecedented rate in size and complexity, outpacing the capacity of existing high-performance compute servers. A modern STA solution that can h... » read more

How AI Will Impact Chip Design And Designers


Experts at the Table: Semiconductor Engineering sat down to discuss the role and impact of AI in chip design with Chuck Alpert, Cadence Fellow; Sathish Balasubramanian, head of product marketing and senior director for custom IC at Siemens EDA; Anand Thiruvengadam, senior director and head of AI product management at Synopsys; Sailesh Kumar, CEO of Baya Systems; Mehir Arora, head of engineering... » read more

3D Heterogeneous Integration System To Accelerate LLMs (Georgia Tech)


A new technical paper titled "A3D-MoE: Acceleration of Large Language Models with Mixture of Experts via 3D Heterogeneous Integration" was published by researchers at Georgia Institute of Technology. Abstract "Conventional large language models (LLMs) are equipped with dozens of GB to TB of model parameters, making inference highly energy-intensive and costly as all the weights need to be ... » read more

Preventing End-to-End Slowdowns In Accelerated Chip Multi-Processors (Cornell University, Intel Labs)


A new technical paper titled "RACER: Avoiding End-to-End Slowdowns in Accelerated Chip Multi-Processors" was published by researchers at Cornell University and Intel Labs. Abstract "Recent chip multiprocessors incorporate several on-chip accelerators, marking the beginning of the Accelerated Chip Multi-Processor (XMP) era in datacenters. Despite the close proximity of accelerators and gener... » read more

Nanoimprint-Based Dielectric Patterning for Fine-Pitch Hybrid Bonding (Seoul National Univ. of Science and Technology)


A new technical paper titled "Hybrid Bonding with Polymeric Interlayer Dielectric Layers Patterned by Nanoimprint Lithography" was published by researchers at Seoul National University of Science and Technology. Abstract "Recent advancements in semiconductor technology have shifted the focus of innovation toward advanced packaging technologies featuring heterogeneous integration. Among thes... » read more

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