Implications of Scalable Neuromorphic Computing (Sandia National Laboratories)


A new technical paper titled "Neuromorphic Computing: A Theoretical Framework for Time, Space, and Energy Scaling" was published by researchers at Sandia National Laboratories. Abstract "Neuromorphic computing (NMC) is increasingly viewed as a low-power alternative to conventional von Neumann architectures such as central processing units (CPUs) and graphics processing units (GPUs), however... » read more

Streamlining Functional Verification For Multi-Die And Chiplet Designs


An Opportunity and a Challenge The manufacturing aspects of multi-die/multi-chiplet designs are often highlighted, but what about verification? Functional correctness and performance of inter-die connections via a standard interface, such as UCIe or a custom inter-die interface, are not guaranteed to meet all system requirements. These interfaces must be verified comprehensively, ensuring co... » read more

When Standards Enable Chiplets


Semiconductor Engineering sat down and discussed the need for standards to enable an ecosystem for chiplets with Mark Kuemerle, vice president of technology for Marvell; Letizia Giuliano, vice president for product marketing and management at Alphawave Semi; Hee-Soo Lee, HSD segment lead for Keysight; Mick Posner, senior product group director for Cadence’s Compute Solutions Group; and Rob Kr... » read more

Blog Review: July 30


Siemens' John McMillan compares 2.5D and 3D-IC technologies and why choosing between them depends on the specific requirements of a product, such as power consumption, thermal constraints, form factor limitations, data bandwidth, and performance-per-watt targets. Cadence's Yeshavanth BN checks out changes in MIPI MPHY 6.0 that increase the data rate and improve the performance of next-genera... » read more

Intrusion Detection Approach for DoS Attacks on Automotive CAN bus (Dumarey Softronix, Politecnico di Torino)


A new technical paper titled "CANDoSA: A Hardware Performance Counter-Based Intrusion Detection System for DoS Attacks on Automotive CAN bus" was published by researchers at Dumarey Softronix and Politecnico di Torino. Abstract "The Controller Area Network (CAN) protocol, essential for automotive embedded systems, lacks inherent security features, making it vulnerable to cyber threats, espe... » read more

CodaCache Last-Level Cache IP


CodaCache Last-Level Cache (LLC) IP, is a configurable, standalone cache designed to enhance system performance, data locality, scalability, power efficiency, and cost-effectiveness in system-on-chip (SoC) designs. It aims to optimize data sharing among computing engines, accelerators, and data processing blocks by improving prefetching mechanisms to lessen reliance on main memory, thereby enha... » read more

Navigating The Quantum Revolution In A Year Of Transformation


In 2025, which the United Nations has designated as the International Year of Quantum Science and Technology, business leaders face a transformative moment where quantum computing emerges from research labs into commercial applications, which early adopters already demonstrating quantum advantage in practical scenarios. This white paper explores how quantum technologies are revolutionizing key ... » read more

Changes In Scan Test Data


Bigger designs with hundred of cores are creating an explosion in the volume of scan test data, significantly bumping up the amount of time spent on test. That raises the cost of test, forcing chipmakers to trade off higher costs with reliability. The solution is to raise the level of abstraction for scan tests, using a bus and packetized data that can run at much higher frequencies than is pos... » read more

Chip Industry Technical Paper Roundup: July 29


New technical papers recently added to Semiconductor Engineering’s library: [table id=458 /] Find more semiconductor research papers here. » read more

Research Bits: July 29


Sort-in-memory Researchers from Peking University and the Chinese Institute for Brain Research developed a sort-in-memory hardware system based on memristors that is tailored for complex, nonlinear sorting tasks. The comparator-free processing-in-memory architecture is built on a one-transistor–one-resistor (1T1R) memristor array, using a Digit Read mechanism that replaces traditional com... » read more

← Older posts Newer posts →