Augmenting Von Neumann’s architecture; VerilogDB; fault-free analog computing; on-die and in-package interconnects; TFLN quantum photonics; memory safe embedded RISC-V; HW-aware failure-detection GPU method; inter-core connected AI chip efficiency; securing against supply chain attacks; HW/SW co-design toolset for RISC-V instructions.
New technical papers recently added to Semiconductor Engineering’s library:
| Name of Paper | Research Organizations |
|---|---|
| Augmenting Von Neumann’s Architecture for an Intelligent Future | TU Munich and Pace University |
| VerilogDB : The Largest, Highest-Quality Dataset with a Preprocessing Framework for LLM-based RTL Generation | University of Florida |
| On-Die And In-Package Interconnects: A 94-page research report on interconnect fundamentals for semiconductor engineers. | Semiconductor Engineering |
| Fault-Free Analog Computing with Imperfect Hardware | The University of Hong Kong, University of Oxford, Hewlett Packard Labs |
| Thin-film lithium niobate quantum photonics: review and perspectives | TU Denmark |
| Efficient Hardware-Assisted Heap Memory Safety for Embedded RISC-V Systems | Inha University, Intel Labs et al. |
| Automatically Retargeting Hardware and Code Generation for RISC-V Custom Instructions | Tampere University |
| A Hardware-Aware Failure-Detection Method for GPU Control-Logic | Hitachi, Osaka University, Kyoto University |
| Elk : Exploring the Efficiency of Inter-core Connected AI Chips with Deep Learning Compiler Techniques | UIUC, Microsoft |
| Security Enclave Architecture for Heterogeneous Security Primitives for Supply-Chain Attacks | University of Florida |
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