40th EMLC Honors Three Decades Of Vision From Dr. Uwe Behringer


The European Mask Lithography Conference (EMLC), an annual event that brings together researchers from around the world to present the latest findings on photomask and lithography technology, returned to Dresden from June 16 to June 18, 2025, and took place for the 40th time – marking a memorable anniversary combined with a premiere. For over 30 years, Dr. Uwe Behringer shaped the conference ... » read more

CMOS 2.0: Layered Logic For The Post-Nanosheet Era


The semiconductor industry has relied on a simple equation for more than five decades — shrink the transistor, pack more onto every wafer, and watch performance soar as costs plummet. While each new node delivered predictable gains in speed, power efficiency, and density, that formula is rapidly running out of steam. As transistors approach single-digit nanometer processes, manufacturing c... » read more

Machine Learning Tools Help Bridge Design-To-Manufacturing Gap


More aggressive feature scaling and increasingly complex transistor structures are driving a steady increase in process complexity, increasing the risk that a specified pattern may not be manufacturable with an acceptable yield. A single layer now requires more process steps, and each of those entails more tunable parameters than ever before. To help manage design risk, foundries provide det... » read more

Five Questions To Ask When Selecting A Temporary Bonding And Debonding System


High-bandwidth memory blocks (HBM) memory, microprocessors, field-programmable gate arrays (FPGA), AI accelerators, and other devices used in advanced system-level packaging all rely on temporary bonding and debonding systems to shrink their footprint. Understanding which properties play the most crucial role in device reliability and efficient production will ensure you are maximizing your yie... » read more

Computer Architecture Extending The Von Neumann Model With A Dedicated Reasoning Unit For Native Artificial General Intelligence (TU Munich, Pace U.)


A new technical paper titled "Augmenting Von Neumann's Architecture for an Intelligent Future" was published by researchers at TU Munich and Pace University. Abstract "This work presents a novel computer architecture that extends the Von Neumann model with a dedicated Reasoning Unit (RU) to enable native artificial general intelligence capabilities. The RU functions as a specialized co-proc... » read more

Accelerating IP Reuse


Semiconductors are no longer monolithic designs developed by a single company. There is more third-party IP from different sources — as many as 1,000 different IPs in a complex SoC — and all of that needs to be integrated and work as one system, something that can require a lot of effort and time. Insaf Meliane, product management and marketing director at Arteris, talks about how the new v... » read more

Blog Review: July 23


Synopsys' Vincent van der Leest and Mike Borza argue that hardware security is critical for providing the foundational trust, physical protection, and performance enhancements necessary to support software security and prevent leaks of sensitive data and cryptographic keys. Siemens' Shetha Nolke explains why stress matters so much in 3D-ICs and why evaluating it isn't as straightforward as i... » read more

Chiplet Ecosystem Slowly Emerges


Experts at the Table: Semiconductor Engineering sat down to discuss progress and remaining challenges for designing with chiplets with Mark Kuemerle, vice president of technology for Marvell; Letizia Giuliano, vice president for product marketing and management at Alphawave Semi; Hee-Soo Lee, HSD segment lead for Keysight; Mick Posner, senior product group director for Cadence’s Compute S... » read more

Largest High-Quality Verilog Dataset for LLM Fine-Tuning (Univ. of Florida)


A new technical paper titled "VerilogDB: The Largest, Highest-Quality Dataset with a Preprocessing Framework for LLM-based RTL Generation" was published by researchers at the University of Florida. Abstract "Large Language Models (LLMs) are gaining popularity for hardware design automation, particularly through Register Transfer Level (RTL) code generation. In this work, we examine the curr... » read more

Fault-Free Matrix for Analog Hardware (The Univ. of Hong Kong, Univ. of Oxford, Hewlett Packard Labs)


A new technical paper titled "Fault-Free Analog Computing with Imperfect Hardware" was published by researchers at The University of Hong Kong, University of Oxford, and Hewlett Packard Labs. Abstract "The surging demand for computational power, particularly for edge computing and AI, drives research into alternative paradigms like analog in-memory computing using memristors. These approach... » read more

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