Geometric-Aware Model Merging Approach To Enhance Instruction Alignment in Chip LLMs (Nvidia)
By Technical Paper Link - 15 Jan, 2025 - Comments: 0

A new technical paper titled "ChipAlign: Instruction Alignment in Large Language Models for Chip Design via Geodesic Interpolation" was published by researchers at NVIDIA Research. Abstract: "Recent advancements in large language models (LLMs) have expanded their application across various domains, including chip design, where domain-adapted chip models like ChipNeMo have emerged. However, ... » read more

Domain Wall Fluctuations in Sliding Ferroelectrics (Cambridge, Argonne)
By Technical Paper Link - 15 Jan, 2025 - Comments: 0

A new technical paper titled "Superconductivity from Domain Wall Fluctuations in Sliding Ferroelectrics" was published by researchers at University of Cambridge and Argonne National Lab. Abstract: "Bilayers of two-dimensional van der Waals materials that lack an inversion center can show a novel form of ferroelectricity, where certain stacking arrangements of the two layers lead to an inter... » read more

Transformation Of Polarons As Tellurene Becomes Thinner
By Technical Paper Link - 15 Jan, 2025 - Comments: 0

A new research paper titled "Thickness-dependent polaron crossover in tellurene" was published by researchers from Rice University, Lawrence Berkeley National Laboratory, MIT, Argonne National Laboratory, ORNL, Purdue University, and Stanford University. Abstract "Polarons, quasiparticles from electron-phonon coupling, are crucial for material properties including high-temperature supercond... » read more

AI Accelerators for Homomorphic Encryption Workloads
By Technical Paper Link - 15 Jan, 2025 - Comments: 0

A new technical paper titled "Leveraging ASIC AI Chips for Homomorphic Encryption" was published by researchers at Georgia Tech, MIT, Google and Cornell University. Abstract: "Cloud-based services are making the outsourcing of sensitive client data increasingly common. Although homomorphic encryption (HE) offers strong privacy guarantee, it requires substantially more resources than compu... » read more

Achieving Successful Timing, Power, And Physical Signoff For Multi-Die Designs
By Synopsys - 15 Jan, 2025 - Comments: 0

Multi-die designs using 2.5D and 3D technologies are increasingly important for a wide range of electronics applications, including high-performance computing (HPC), artificial intelligence (AI), automotive, and mobile. The multi-die architecture enables designers to mix dies from different foundries and technology nodes, including existing dies from previous projects. The resulting density and... » read more

How Engineering Simulation Drives Impact for Sustainability
By Ansys - 15 Jan, 2025 - Comments: 0

For decades, engineering simulation has been the engineer’s Swiss Army knife for improving the speed and cost of developing new products as well as for bringing product performance to the next level. This report reveals that while simulation has already made a significant contribution to advancing sustainability, there is still so much potential to make an even greater impact. In the conte... » read more

How Google And Intel Use Calibre DesignEnhancer To Reduce IR Drop And Improve Reliability
By Siemens EDA - 15 Jan, 2025 - Comments: 0

In the fast-paced world of semiconductor design, achieving both Design Rule Check (DRC) clean layouts and optimal electrical performance is crucial for minimizing design iterations, reducing time-to-market and ensuring product reliability. This paper explores how the Calibre DesignEnhancer (DE) analysis-based, signoff-quality EMIR solution helps design teams meet these challenges by enhancing p... » read more

AI Won’t Replace Subject Matter Experts
By Adam Kovac - 15 Jan, 2025 - Comments: 0

Experts at The Table: The emergence of LLMs and other forms of AI has sent ripples through a number of industries, raising fears that many jobs could be on the chopping block, to be replaced by automation. Whether that’s the case in semiconductors, where machine learning has become an integral part of the design process, remains to be seen. Semiconductor Engineering sat down with a panel of e... » read more

Why Your Data Center Needs a Digital Twin
By Cadence - 15 Jan, 2025 - Comments: 0

The global digital twin market is on a rapid ascent, projected to skyrocket from $11.51 billion in 2023 to $137.67 billion by 2030. Spanning industries from aerospace to healthcare, digital twins are becoming an essential tool for efficient management. But what is a digital twin? Essentially, it’s a digital replica of any real-world entity—a product, system, or process—used for simulation... » read more

Blog Review: Jan. 15
By Jesse Allen - 15 Jan, 2025 - Comments: 0

Siemens EDA's Stephen V. Chavez argues that the placement of decoupling capacitors on a PCB can make or break a design's power delivery system and provides some best practices and design considerations, such as ensuring even distribution on a board rather than crowding them around chips. Synopsys' Stelios Diamantidis predicts that in 2025, AI agents will begin collaborating with other AI age... » read more

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