Outlook 2025: Embracing Chiplets


The semiconductor industry is rapidly evolving, and as we look towards 2025, chiplets are at the forefront of this transformation. The shift from traditional monolithic system-on-chip (SoC) designs to chiplet-based architectures is gaining momentum, driven by the need to meet ever-increasing computing demands. This evolution is not just a trend; it represents a fundamental change in how we appr... » read more

The Xpedition Flow


Comprehensive approach to designing electronics The complexities of modern PCB design necessitate a comprehensive approach that integrates various aspects of the entire design through manufacturing flow. The ideal design flow requires seamless cooperation and synergy across various domains, including electrical, mechanical, software, systems, test, and manufacturing. Xpedition provides a gr... » read more

Backpropagation Algorithm On Neuromorphic Spiking HW (U. Of Zurich, ETH Zurich, LANL)


A new technical paper titled "The backpropagation algorithm implemented on spiking neuromorphic hardware" was published by University of Zurich, ETH Zurich, Los Alamos National Laboratory, Royal Institution, London, et al. "This study presents a neuromorphic, spiking backpropagation algorithm based on synfire-gated dynamical information coordination and processing implemented on Intel’s Lo... » read more

Chip Industry Technical Paper Roundup: Nov. 25


New technical papers recently added to Semiconductor Engineering’s library: [table id=386 /] » read more

GenAI + Semiconductors + Humanity


Silicon Catalyst held its 2024 Semiconductor Industry Forum in Mountain View, CA, at the Computer History Museum on November 13th. Richard Curtin, managing partner for Si Catalyst, opened the event by thanking David House, vice chair of the Board at the Computer History Museum and creator of the 4004 processor, and the CHM staff for hosting the event. Richard talked about the start of se... » read more

Why Silicon IP Has Become the Foundation of Modern SoC Design


Addressing challenges of using silicon IP, tracking IP cores, and taking advantage of the flexibility of modular design requires a proven process. It also requires a state-of-the-art IP management system and modular design roadmap that will lead to success in silicon. Keysight has identified 6 steps to effective IP management based on best practices and customer experiences. Read more here. » read more

Research Bits: Nov. 25


3D-printed ESD protection Researchers from Lawrence Livermore National Laboratory developed a printable elastomeric silicone foam for electronics packaging that provides both mechanical and electrostatic discharge (ESD) protection. The team used a 3D printing technique called direct ink writing (DIW), an extrusion process in which a paste with controlled rheological properties such as elast... » read more

Direct-To-Chip Liquid-Cooled Data Centers (Binghamton, Nvidia)


A new technical paper titled "Parameters of performance: A deep dive into liquid-to-air CDU assessment" was published by researchers at Binghamton University-SUNY and NVIDIA. Abstract: "The rapid growth in data center workloads and the increasing complexity of modern applications have led to significant contradictions between computational performance and thermal management. Traditional air... » read more

Chip Industry Week In Review


SK hynix started mass production of 1-terabit  321-high NAND, with availability scheduled for the first half of next year. Rapidus will receive an additional ¥200 billion yen ($1.28B) from the Japanese government beginning in fiscal year 2025, reports Nikkei. This is on top of ¥920 billion yen ($5.98B) Rapidus has already received from the government in support of its goal to reach commer... » read more

Analysis Of Multi-Chiplet Package Designs And Requirements For Production Test Simplification


In recent years there has been a sharp rise of multi-die system designs. Numerous publications targeting a large variety of applications exist in the public domain. One presentation [2] on the IEEE’s website does a good job of detailing the anecdotal path of multi-die systems by way of chiplet building blocks integrated within a single package [2]. The presentation includes references to a ha... » read more

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