A Design And Benchmarking Study Of CAM At 7nm In The Context Of Similarity Search Applications (Georgia Tech)


A technical paper titled “Cross-layer Modeling and Design of Content Addressable Memories in Advanced Technology Nodes for Similarity Search” was published by researchers at the Georgia Institute of Technology. Abstract: "In this paper we present a comprehensive design and benchmarking study of Content Addressable Memory (CAM) at the 7nm technology node in the context of similarity search... » read more

Adapting To Evolving IC Requirements


As chip designs become increasingly heterogeneous and domain-specific, packing a device with one-size-fits-all chips or chiplets doesn't make sense. The key is rightsizing different components based on real workloads, so they don't waste power when there is too little utilization of logic, and so they don't struggle to complete tasks because they are undersized. Jayson Bethurem, vice president ... » read more

Research Bits: May 7


High-temperature memory Researchers from the University of Pennsylvania and Air Force Research Laboratory demonstrated memory technology capable of enduring temperatures as high as 600° Celsius for more than 60 hours while retaining stability and reliability. The non-volatile memory device consists of a metal–insulator–metal structure, incorporating nickel and platinum electrodes with a 4... » read more

Chip Industry Technical Paper Roundup: May 7


New technical papers added to Semiconductor Engineering’s library this week. [table id=223 /] More ReadingTechnical Paper Library home » read more

Can Models Created With AI Be Trusted?


EDA models that are created using AI need to pass more stringent quality and cost benefit analysis compared to many AI applications in the broader industry. Money is hanging on the line if AI gets it wrong, and all the associated costs must be factored into the equation. Models are some of the most expensive things a development team can create, and it is important to understand the value th... » read more

Optimizing Offload Performance In Heterogeneous Multi-Processor SoCs (ETH Zurich)


A technical paper titled “Optimizing Offload Performance in Heterogeneous MPSoCs” was published by researchers at ETH Zurich. Abstract: "Heterogeneous multi-core architectures combine a few "host" cores, optimized for single-thread performance, with many small energy-efficient "accelerator" cores for data-parallel processing, on a single chip. Offloading a computation to the many-core acc... » read more

Chip Industry Week In Review


Samsung and Synopsys collaborated on the first production tapeout of a high-performance mobile SoC design, including CPUs and GPUs, using the Synopsys.ai EDA suite on Samsung Foundry's gate-all-around (GAA) process. Samsung plans to begin mass production of 2nm process GAA chips in 2025, reports BusinessKorea. UMC developed the first radio frequency silicon on insulator (RF-SOI)-based 3D IC ... » read more

Distributing RTL Simulation Across Thousands Of Cores On 4 IPU Sockets (EPFL)


A technical paper titled “Parendi: Thousand-Way Parallel RTL Simulation” was published by researchers at EPFL. Abstract: "Hardware development relies on simulations, particularly cycle-accurate RTL (Register Transfer Level) simulations, which consume significant time. As single-processor performance grows only slowly, conventional, single-threaded RTL simulation is becoming less practical... » read more

A Micro Light-Emitting Transistor With An N-Channel GaN FET In Series With A GaN LED


A technical paper titled “Tunnel Junction-Enabled Monolithically Integrated GaN Micro-Light Emitting Transistor” was published by researchers at the Ohio State University and Sandia National Laboratory. Abstract: "GaN/InGaN microLEDs are a very promising technology for next generation displays. Switching control transistors and their integration are key components in achieving high-perfor... » read more

Voltage Reference Architectures For Harsh Environments: Quantum Computing And Space


A technical paper titled “Cryo-CMOS Voltage References for the Ultrawide Temperature Range From 300 K Down to 4.2 K” was published by researchers at Delft University of Technology, QuTech, Kavli Institute of Nanoscience Delft, and École Polytechnique Fédérale de Lausanne (EPFL). Abstract: "This article presents a family of sub-1-V, fully-CMOS voltage references adopting MOS devices in ... » read more

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