The Race Begins For Much Bigger Abstractions In Data Centers


Key Takeaways Data center build-out is enabling much larger and more complex abstractions. Competition is building for digital/virtual twins across multiple industry segments, including automotive, aerospace, and chip manufacturing. AI, and particularly AI agents, will play a significant role in sorting through data to find potential trouble spots. The frenzy of new data cen... » read more

One-on-One With proteanTecs CEO Shai Cohen


The acceleration of technology is unprecedented: AI data centers, edge build-out, robotics, photonics, quantum, multi-die assemblies. Semiconductor Engineering Editor in Chief Ed Sperling talks with proteanTecs CEO Shai Cohen about what's changing and what impact it will have. Click here to listen. » read more

New Class Of Semiconductors Made Of Germanium-Tin Alloy (University of Edinburgh et al.)


A new technical paper "High Pressure and Compositionally Directed Route to a Hexagonal GeSn Alloy Class" was published by researchers at the University of Edinburgh, GFZ Helmholtz Centre for Geosciences, the University of Lille, Grenoble Alpes University, the University of Bayreuth and the European Synchrotron facility. Abstract "Despite their electronic dominance, cubic diamond structure... » read more

Less Power and Higher Performance With A Nanolaser With Extreme Dielectric Confinement (DTU)


A new technical paper titled "A nanolaser with extreme dielectric confinement" was published by researchers at Technical University of Denmark (DTU). Abstract "The interaction between light and matter can be enhanced by spatially concentrating the light field and extending photon dwell time. Plasmonic structures can provide strong light confinement but suffer from ohmic losses. Recent adv... » read more

Chip Industry Technical Paper Roundup: Feb. 16


New technical papers recently added to Semiconductor Engineering’s library: [table id=523 /] Find more semiconductor research papers here. » read more

Carrier Mapping in Sub-2nm Node NSFETs with SSRM (imec, KU Leuven)


Researchers from imec and KU Leuven published "Carrier Mapping in Sub-2nm Node Nanosheet Transistors with Scanning Spreading Resistance Microscopy." Abstract "As the semiconductor industry transitions to gate-all-around architectures such as Nanosheet-FETs (NSFETs) for the 2nm node and beyond, controlling parasitic resistance through precise junction engineering is fundamental. This requi... » read more

LLM-Based Learning Platform For Chip Design Education (RPTU)


RPTU University of Kaiserslautern-Landau researchers published "From RTL to Prompt Coding: Empowering the Next Generation of Chip Designers through LLMs." Abstract "This paper presents an LLM-based learning platform for chip design education, aiming to make chip design accessible to beginners without overwhelming them with technical complexity. It represents the first educational platform... » read more

Automated MLIR-based HLS framework That Generates FPGA HW Designs From A Variety of CNN Layers (TU Dresden)


TU Dresden researchers published "MING: An Automated CNN-to-Edge MLIR HLS framework." Abstract "Driven by the increasing demand for low-latency and real-time processing, machine learning applications are steadily migrating toward edge computing platforms, where Field-Programmable Gate Arrays (FPGAs) are widely adopted for their energy efficiency compared to CPUs and GPUs. To generate high... » read more

CNT Nano Sandpaper For Atomic-Level Polishing (KAIST)


KAIST researchers published "Carbon nanotube sandpaper for atomic-precision surface finishing." Abstract "Sandpapers, also known as coated abrasives, have served as the most familiar surface finishing tools since their first invention in the 13th century. However, they remain unsuitable for advanced industries requiring nanometer-level precision due to limitations in abrasive uniformity a... » read more

A Test Generation Procedure Targeting Subcircuits With High Susceptibilities To Aging (Purdue University)


A technical paper titled "Test Generation for Subcircuits with High Functional Switching Activities" was published by Irith Pomeranz at Purdue University. Abstract "Chip aging results in defects that are initially likely to appear as delay faults. The susceptibility of a delay fault to aging can be assessed based on the layout or the functional workload at the fault site. The key contribu... » read more

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