A technical paper titled “Test Generation for Subcircuits with High Functional Switching Activities” was published by Irith Pomeranz at Purdue University.
Abstract
“Chip aging results in defects that are initially likely to appear as delay faults. The susceptibility of a delay fault to aging can be assessed based on the layout or the functional workload at the fault site. The key contribution of this article is based on the observation that when fault sites with high susceptibilities to aging are included in a contiguous gate-level subcircuit, the subcircuit as a whole is susceptible to aging. Moreover, a test that detects more of the delay faults in the subcircuit exercises the subcircuit better, and is more likely to bring out the effects of aging. Motivated by this observation, the key contribution of this article is a gate-level scan-based test generation procedure that targets subcircuits with high susceptibilities to aging. The susceptibility to aging is assessed based on the functional switching activity that occurs under functional sequences. The underlying target faults are single transition faults. The test generation procedure augments a conventional transition fault test set with tests that improve the coverage of subcircuits with high susceptibilities to aging. Experimental results for benchmark circuits demonstrate significant improvements in the coverage of subcircuits with high susceptibilities to aging, and the numbers of tests needed for augmenting a conventional transition fault test set to achieve these improvements.”
Find the technical paper here. February 2026.
I. Pomeranz, “Test Generation for Subcircuits with High Functional Switching Activities,” in IEEE Access, doi: 10.1109/ACCESS.2026.3660213.
Leave a Reply