Week In Review: Design, Low Power


Tools & IP MIPS announced its first products based on the RISC-V ISA. The eVocore IP cores are designed to provide a flexible foundation for heterogeneous compute, supporting combinations of eVocore processors as well as other accelerators, with a Coherence Manager that maintains L2 cache and system-level coherency between all cores, main memory, and I/O devices. They target high-performan... » read more

Week In Review: Auto, Security, Pervasive Computing


Automotive, mobility Fraunhofer IIS has opened a five-kilometer (3.11-mile) 5G test bed for automotive 5G applications near the city of Rosenheim in Bavaria, Germany. A closed 5G network with multiple base stations covers the test track, where connected cars can be tested under real conditions. “The automotive test bed is designed specially for developers and users that want to test new conn... » read more

DRAM Choices Becoming Central Design Considerations


Chipmakers are paying much closer attention to various DRAM options as they grapple with what goes on-chip or into a package, elevating attached memory to a critical design element that can affect system performance, power, and cost. These are increasingly important issues to sort through with a number of tradeoffs, but the general consensus is that to reach the higher levels of performance ... » read more

The Challenge Of Optimizing Chip Architectures For Workloads


It isn't possible to optimize a workload running on a system just by looking at hardware or software separately. They need to be developed together and intricately intertwined, an engineering feat that also requires bridging two worlds with have a long history of operating independently. In the early days of computing, hardware and software were designed and built by completely separate team... » read more

Chiplets: Current Status


Recent weeks have seen a number of interesting developments in the area of chiplets. An increasing number of products based on chiplets have been brought to market, especially in the processors segment. For example, Apple and AMD now have processors with chiplets on the market and under production in high volumes. On one hand, this means that sufficient production capacity has now been built up... » read more

New Robots Require New Ways To Think About Processors


We’re on the cusp of a revolution in robots. After years of relatively moderate growth, sales of commercial and industrial robots are slated to grow by 25% to 35% per year over the next decade, according to Boston Consulting Group, and could reach $260 billion by 2030 to meet the demands of manufacturers, retailers and others to streamline supply chains, enhance safety and boost productivity.... » read more

Improving PPA With AI


AI/ML/DL is starting to show up in EDA tools for a variety of steps in the semiconductor design flow, many of them aimed at improving performance, reducing power, and speeding time to market by catching errors that humans might overlook. It's unlikely that complex SoCs, or heterogeneous integration in advanced packages, ever will be perfect at first silicon. Still, the number of common error... » read more

A Sea Change In Signaling With PCIe 6.0


PCI Express (PCIe) is one of those standards from the PC world, like Ethernet, that has proliferated far beyond its original application space. Thanks to its utility and economies of scale, PCIe has found a place in applications in IoT, automotive, test and measurement, medical, and more. As it has scaled, PCIe has pushed NRZ signaling to higher and higher levels reaching 32 gigatransfers per s... » read more

What’s In A Name(space)? Optimizing SSD Controller Performance And Verification


Solid state drives (SSDs) have come to the forefront as a promising solution for today and tomorrow’s immense data transfer and storage demands. And SSDs themselves are constantly evolving with upgrades of their critical components to provide higher access speeds. One such component for the NVMe specification is created by the division of non-volatile memory (NVM) into what are commonly known... » read more

Meeting 112 SerDes Based System Design Challenges


The need for higher bandwidth networking equipment as well as connectivity in the cloud and hyperscale data centers is driving the switch technology transition from 25Tb/s (terabytes) to 51Tb/s and soon to 100Tb/s. The industry has chosen Ethernet to drive the switch market, using 112G SerDes or PHY technology today and 224G SerDes in the future. This article describes how designers can overcom... » read more

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