Amdahl Limits On AI


Software and hardware both place limits on how fast an application can run, but finding and eliminating the limitations is becoming more important in this age of multicore heterogeneous processing. The problem is certainly not new. Gene Amdahl (1922-2015) recognized the issue and published a paper about it in 1967. It provided the theoretical speedup for a defined task that could be expected... » read more

Can Coherent Optics Reduce Data-Center Power?


As optical bandwidth requirements increase, system designers are turning to “coherent” modulation schemes that can place more data on the same laser light, and lower power over long connections. A newer question is whether those savings could be achieved for short connections within data centers, as well. “Coherent is the direction everything's moving, because for a given system and... » read more

Scaling DDR5 RDIMMs To 5600 MT/s


Looking forward to 2022, the first of the DDR5-based servers will hit the market with RDIMMs running at 4800 megatransfers per second (MT/s). This is a 50% increase in data rate over top-end 3200 MT/s DDR4 RDIMMs in current high-performance servers. DDR5 memory incorporates a number of innovations, such as Decision Feedback Equalization (DFE), and a new DIMM architecture which enable that speed... » read more

Choose The Right Sensors For Autonomous Vehicles


When the world’s first “motorwagen” was introduced in 1885, the notion that a car would one day drive itself was laughable. Today, assisted and autonomous vehicles are the reality of an age where digital sensors can outperform human ability to perceive motion, distance, and speed. When used together, sensor technologies including camera, lidar, radar, and ultrasonic give vehicles one... » read more

Innovations In Sensor Technology


Sensors are the “eyes” and “ears” of processors, co-processors, and computing modules. They come in all shapes, forms, and functions, and they are being deployed in a rapidly growing number of applications — from edge computing and IoT, to smart cities, smart manufacturing, hospitals, industrial, machine learning, and automotive. Each of these use cases relies on chips to capture d... » read more

The Future Of Smart Cameras Is 64-Bit Processing


The future of smart camera technology brings with it profound transformations in the way we interact with each other and the world around us. From smart cities that are safer and more efficient to rainforests that are monitored for illegal logging, the increasing need for advanced vision technology is growing. Diverse and complex use cases leveraging artificial intelligence (AI) and machine lea... » read more

Moving From AMBA ACE to CHI For Coherency


Introduced back in 2011, ACE (AXI Coherency Extensions) grew from the existing AXI protocol to satisfy the cache coherency maintenance demands of SoCs with multi core processors and shared caches in smart phones, mobile computers, and servers. It added new channels for cache communication, extra signals to allow new transaction for coherency support, and five state model for caches. AXI + A... » read more

Run Realistic Software For Full Chip Power Signoff


In the real world, the demand for AI chips is driving the trend towards bigger, smarter, and faster SoC designs. Consequently, low-power design, analysis, verification, and power signoff challenges are not getting any easier as chip designs deploy increasingly smaller geometries that dissipate more and more power. Despite this dilemma, the quest for further power reductions continues apace. ... » read more

The Physics Of Ports And Associated Ground For EM Simulators Serving RF Designs


The use of ports in electromagnetic (EM) simulators has evolved and matured over the years to make real-world design simulations practical. Having a foundational understanding of ports provides an intuitive skill in their proper selection and use in conjunction with circuit simulation. In this white paper, we examine ports common to EM simulators, which are the most common simulators for microw... » read more

Shifting Left In P&R With In-Design Signoff Fill For Faster And More Accurate Tapeouts


Place and route (P&R) engineers are always on the lookout for ways to optimize their design flows to ensure designs meet their design power, performance, and area (PPA) goals while also hitting tapeout deadlines. The introduction of the Calibre RealTime Digital interface made Calibre nmDRC and Calibre nmDRC Recon design rule checking (DRC) verification available during the P&R process t... » read more

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