End-To-End Traceability
By Ed Sperling - 29 Nov, 2021 - Comments: 0

Despite standards such as ISO 26262 and IEC 61508, there are still disconnects and gaps in the supply chain and design-through-manufacturing flows. Kurt Shuler, vice president of marketing at Arteris IP, digs into what's missing, why changes made in one area are not reflected in other areas and throughout the product lifecycle, and why various different phases of the flow don't always match up ... » read more

Missing Interposer Abstractions And Standards
By Brian Bailey - 29 Nov, 2021 - Comments: 0

The design and analysis of an SoC based on an interposer is not for the faint of heart today, but the industry is aware of the challenges and is attempting to solve them. Until that happens, however, it will be a technique that only large companies can deploy because they need to treat everything almost as if it were a single die. The construction of large systems uses techniques, such as ab... » read more

Manufacturing Bits: Nov. 24
By Mark LaPedus - 24 Nov, 2021 - Comments: 0

Tiny MEMS gyroscope CEA-Leti and Politecnico di Milano (POLIMI) have developed the world’s smallest MEMS gyroscope. Based on a nano-resistive sensing technology, the gyroscope enables a navigation-grade performance with a sensor footprint of only 1.3mm2. The tiny gyroscope is targeted for high-volume markets like automotive and others. The technology was reported in a paper, entitled “1... » read more

Blog Review: Nov. 24
By Jesse Allen - 24 Nov, 2021 - Comments: 0

Cadence's Paul McLellan introduces the theory and practice of datapath formal verification and explores two use cases of dot-product accumulate systolic design and hashing design. Siemens EDA's Rich Edelman shows that constructing an in-order UVM scoreboard doesn't have to be a difficult or complex task, and certainly simpler than replacing a laptop's keyboard. Synopsys' Gordon Cooper con... » read more

Power/Performance Bits: Nov. 24
By Jesse Allen - 24 Nov, 2021 - Comments: 0

Flexible, low power phase-change memory Engineers at Stanford University created a flexible phase-change memory. The non-volatile phase-change memory device is made up of germanium, antimony, and tellurium (GST) between two metal electrodes. 1s and 0s represent measurements of electrical resistance in the GST material. “A typical phase-change memory device can store two states of resis... » read more

The development of integrated circuits based on two-dimensional materials
By Technical Paper Link - 23 Nov, 2021 - Comments: 0

Abstract Two-dimensional (2D) materials could potentially be used to develop advanced monolithic integrated circuits. However, despite impressive demonstrations of single devices and simple circuits—in some cases with performance superior to those of silicon-based circuits—reports on the fabrication of integrated circuits using 2D materials are limited and the creation of large-scale circu... » read more

Product Lifecycle Management For Semiconductors
By Brian Bailey - 23 Nov, 2021 - Comments: 1

Product lifecycle management (PLM) and the semiconductor industry have always been separate, but pressure is growing to integrate them. Automotive, IIoT, medical, and other industries see that as the only way to manage many aspects of their business, and as it stands, semiconductors are a large black box in that methodology. The technology space is driven by a mix of top down and bottom-up p... » read more

Structural Vs. Functional
By Brian Bailey - 23 Nov, 2021 - Comments: 0

When working on an article about PLM and semiconductors, I got to review a favorite topic from my days in EDA development – verification versus validation. I built extensive presentations around it and tried to persuade people within the EDA industry, as well as customers, about the advantages of doing a top-down functional modeling and analysis. The V diagram that everyone uses is flawed and... » read more

Advanced Packaging Shifts Design Focus To System Level
By Ann Mutschler - 23 Nov, 2021 - Comments: 0

Growing momentum for advanced packaging is shifting design from a die-centric focus toward integrated systems with multiple die, but it's also straining some EDA tools and methodologies and creating gaps in areas where none existed. These changes are causing churn in unexpected areas. For some chip companies, this has resulted in a slowdown in hiring of ASIC designers and an uptick in new jo... » read more

Gaps In The AI Debug Process
By Brian Bailey - 23 Nov, 2021 - Comments: 0

When an AI algorithm is deployed in the field and gives an unexpected result, it's often not clear whether that result is correct. So what happened? Was it wrong? And if so, what caused the error? These are often not simple questions to answer. Moreover, as with all verification problems, the only way to get to the root cause is to break the problem down into manageable pieces. The semico... » read more

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