Manufacturing Bits: May 19

By Mark LaPedus - 19 May, 2020 - Comments: 0

Virus simulations Using an advanced building simulator and testbed, Lawrence Berkeley National Laboratory (Berkeley Lab) is launching a study of the risk of airborne transmission of viruses in buildings. Researchers will also explore the ways to mitigate those risks. The experiments will take place in Berkeley Lab’s FLEXLAB, which is an advanced building simulator. Used by builders, archi... » read more

Choosing Between CCIX And CXL

By Ed Sperling - 19 May, 2020 - Comments: 0

Semiconductor Engineering sat down to the discuss the pros and cons of the Compute Express Link (CXL) and the Cache Coherent Interconnect for Accelerators (CCIX) with Kurt Shuler, vice president of marketing at Arteris IP; Richard Solomon, technical marketing manager for PCI Express controller IP at Synopsys; and Jitendra Mohan, CEO of Astera Labs. What follows are excerpts of that conversati... » read more

Power/Performance Bits: May 19

By Jesse Allen - 19 May, 2020 - Comments: 0

Neuromorphic magnetic nanowires Researchers from the University of Texas at Austin, University of Texas at Dallas, and Sandia National Laboratory propose a neuromorphic computing method using magnetic components. The team says this approach can cut the energy cost of training neural networks. "Right now, the methods for training your neural networks are very energy-intensive," said Jean Ann... » read more

Spiking Neural Networks: Research Projects or Commercial Products?

By Bryon Moyer - 18 May, 2020 - Comments: 2

Spiking neural networks (SNNs) often are touted as a way to get close to the power efficiency of the brain, but there is widespread confusion about what exactly that means. In fact, there is disagreement about how the brain actually works. Some SNN implementations are less brain-like than others. Depending on whom you talk to, SNNs are either a long way away or close to commercialization. Th... » read more

Week In Review: Manufacturing, Test

By Mark LaPedus - 15 May, 2020 - Comments: 0

Chipmakers TSMC has announced its intention to build and operate an advanced semiconductor fab in the U.S. The fab, to be built in Arizona, will utilize TSMC’s 5nm technology and will produce 20,000 wafers per month. TSMC’s total spending on this project will be approximately $12 billion from 2021 to 2029. Construction is planned to start in 2021 with production targeted to begin in 202... » read more

Week In Review: Design, Low Power

By Jesse Allen - 15 May, 2020 - Comments: 0

Tools & IP Synopsys released a range of IP for TSMC's 5nm process technology. It includes interface PHY IP such as 112G/56G Ethernet, Die-to-Die, PCIe 5.0, CXL, and CCIX; memory interface IP for DDR5, LPDDR5, and HBM2/2E; die-to-die PHYs for 112G USR/XSR connectivity and High-Bandwidth Interconnect; and foundation IP including logic libraries, multi-port memory compilers, and TCAMs. Sma... » read more

Week In Review: Auto, Security, Pervasive Computing

By SE Staff - 15 May, 2020 - Comments: 0

Security Ninety-one percent of commercial applications contain outdated or abandoned open-source components —a security threat, says Synopsys in its recently released report 2020 Open Source Security and Risk Analysis (OSSRA). In the fifth annual edition of the report, Synopsys’ research team in its Cybersecurity Research Center (CyRC) found that 99% of the 1,250 commercial codebases revie... » read more

The Other Storage Race

By Ed Sperling - 15 May, 2020 - Comments: 2

Tesla's push to extend the life of lithium ion batteries used in cars by repurposing them for less-intensive applications could have a major impact on the business model for a whole slew of other markets. As anyone with a smartphone knows, batteries degrade over time. A new phone holds a charge longer than one that has been in use for several years, but in the case of a smartphone that's gen... » read more

Power Management And Integration Of IPs In SoCs: Part 2

By Progyna Khondkar - 14 May, 2020 - Comments: 0

Most IP are available as either soft or hard macros. But both pose immense challenges. This is especially so when integrating them into low power designs and conducting power aware (PA) verification, because the majority of IP are self-contained and pre-verified at the block level and they must be preserved in their entirety when integrated or verified in the SoC level. Part one of this two ... » read more

Layout Generators For Artificial Intelligence Hardware Design

By Benjamin Prautsch - 14 May, 2020 - Comments: 0

Artificial intelligence (AI) is a powerful tool that offers great convenience in many areas of life. In addition to improving Internet searches and online shopping, it enables driver assistance systems that can save lives, for example. AI in its various forms is the essential tool for such applications, and it can be expected to show a similar development as microelectronics did. Although AI... » read more

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