Super Planarizing Material For Trench And Via Arrays

By Brewer Science - 21 May, 2020 - Comments: 0

As device design scales and becomes more complex, fine control of patterning and transfer steps is integral. Planarization of deep trenches and via arrays has always been a challenge. Aspect ratios continue to increase while critical dimensions shrink, and typical trench fill schemes are no longer able to meet the fill and planarization requirements. Traditional design of spin-on carbon (SOC) m... » read more

Best Practices In Business Continuity Planning

By Heidi Hoffman - 21 May, 2020 - Comments: 0

Cameron Burks, head of Global Security, Enterprise Business Resiliency and Health, Environment & Safety with Adobe Systems, and a member of the White House Task Force for COVID-19 response, briefed members of SEMI’s IT Leadership (ITL) and Environment, Health & Safety (EHS) groups on April 20, 2020, on enterprise resiliency principals specific to the current COVID-19 crisis. Burk... » read more

Fan-Out Wafer-Level Packaging And Copper Electrodeposition

By Steven T. Mayer - 21 May, 2020 - Comments: 0

By Steven T. Mayer, Bryan Buckalew, and Kari Thorkelsson As integrated circuit designers bring more sophisticated chip functionality into smaller spaces, heterogeneous integration, including 3D stacking of devices, becomes an increasingly useful and cost-effective way of mixing and connecting various functional technologies. One of the heterogeneous integration platforms gaining increased ac... » read more

Consideration Of Missing Defect Suppression Technique In EUV Hole Patterning

By TEL - 21 May, 2020 - Comments: 0

This study focused on the defect behavior analysis with CD variation on EUV via hole pattern using photolithographic process and etch transfer performance. While defect requirements are not as stringent for memory devices, logic devices must be defect-free. Currently, a defect which comes from the process or material can only be detected by top-down inspection approach, however, it is difficult... » read more

Compute-In Memory Accelerators Up-End Network Design Tradeoffs

By Katherine Derbyshire - 21 May, 2020 - Comments: 0

An explosion in the amount of data, coupled with the negative impact on performance and power for moving that data, is rekindling interest around in-memory processing as an alternative to moving data back and forth between the memory and the processor. Compute-in-memory (CIM) arrays based on either conventional memory elements like DRAM and NAND flash, as well as emerging non-volatile memori... » read more

Cleaning Data For Final Test

By Ed Sperling - 20 May, 2020 - Comments: 0

John O’Donnell, CEO of yieldHUB, talks about why data integrity is so critical for final test, what can cause it to be less-than-perfect, what’s needed to improve the quality of that data, and how that impacts the overall yield in a fab. » read more

Remotely Performing IC Validation

By Tommy Mullane - 20 May, 2020 - Comments: 0

One of the key stages in designing any chip is the testing you do when you get the first silicon back. This is where you finally see the results of all your careful work and determine whether the chip is performing as designed, and as simulation told you it would. This is known as IC validation. The focus of validation is on functional test – checking that the chip in silicon meets the origin... » read more

Blog Review: May 20

By Jesse Allen - 20 May, 2020 - Comments: 0

Synopsys' Jonathan Knudsen demystifies fuzzing techniques and why the process of sending targeted, intentionally invalid data is important to determining security. Mentor's Chris Spear explains both the potential benefits and challenges of the UVM Configuration Database and guidelines to improve performance. Cadence's Paul McLellan continues the look back at mobile history with the beginn... » read more

Design For Narrowband IoT

By Ann Mutschler - 20 May, 2020 - Comments: 0

Most low-power chips are designed with the assumption that batteries can be recharged or replaced, but there is a whole set of IoT devices under development that are expected to be always-on, communicate over a cellular infrastructure, and remain functional on a coin-sized lithium-ion battery for a decade or more. Welcome to the world of Narrowband IoT (NB-IoT), a 3GPP standard (also known a... » read more

Rising Packaging Complexity

By Ed Sperling - 19 May, 2020 - Comments: 1

Synopsys’ Rita Horner looks at the design side of advanced packaging, including how tools are chosen today, what considerations are needed for integrating IP while maintaining low latency and low power, why this is more complex in some ways than even the most advanced planar chip designs, and what’s still missing from the tool flow. » read more

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