Enabling Chiplet And Co-Packaged Optics Architectures With 112G XSR SerDes
By Suresh Andani - 14 May, 2020 - Comments: 0

Conventional chip designs are struggling to achieve the scalability, as well as power, performance, and area (PPA), that are demanded of leading-edge designs. With the slowing of Moore’s Law, high complexity ASICs increasingly bump up against reticle limits. The demise of Dennard scaling means power consumption is a growing challenge. In this context, disaggregated architectures such as chipl... » read more

The Need For 3D IC Packaging And Design Evolution
By Rita Horner - 14 May, 2020 - Comments: 0

If you are familiar with Moore’s Law, you’ve probably read pronouncements that the premise of transistor counts doubling each year is reaching a wall due to complex process technologies and device physics limitations. Regardless of how well transistor counts continue to scale, market segments continue to drive the thirst for more compute performance and fast time to markets. Artificial i... » read more

iSIM With IoT SAFE For Seamless Authentication From Chip To Cloud
By Paul Bradley - 14 May, 2020 - Comments: 0

When transferring data over mobile networks, IoT devices need to exchange that data securely and establish trust with a public or edge cloud in a way that’s seamless, scalable and easy to manage. IoT SAFE (IoT SIM Applet For Secure End-2-End Communication) enables IoT device manufacturers and IoT service providers to leverage the SIM (Subscriber Identity Module) as a robust, scalable and stan... » read more

Choosing Between Static and Dynamic Shapes
By Tyler Lockman - 14 May, 2020 - Comments: 0

That title might be a touch misleading. We’re not here to talk about why to convert shapes between static and dynamic. Rather, I want to talk about why you should NOT be doing this. Every design has some conductor shapes in it (or at least a very large percentage of them). What style to use is a choice that will impact performance through your entire flow; let the shape’s purpose guide you.... » read more

Monitoring For In-Die Process Speed Detection
By Richard McPartland - 14 May, 2020 - Comments: 0

Chip designers working on advanced nodes typically include a fabric of sensors spread across the die for a number of very specific reasons. In this, the second of a three-part blog series, we explore some of the key applications and benefits of these types of sensing solutions. In this installment, the focus is In-Die Process Speed Detection and why understanding in-chip process speed detecti... » read more

Low-Power Analog
By Brian Bailey - 14 May, 2020 - Comments: 3

Analog circuitry is usually a small part of a large SoC, but it does not scale in the same way as digital circuitry under Moore's Law. The power consumed by analog is becoming an increasing concern, especially for battery-operated devices. At the same time, little automation is available to help analog designers reduce consumption. "Newer consumer devices, like smartphones and wearables, alo... » read more

Doing More For Less With Upgraded LON Networks
By Apurba Pradhan - 14 May, 2020 - Comments: 0

At Adesto, we talk a lot about the importance of embracing all IoT communications protocols. We believe that our customers and their customers can derive great benefit from building and industrial control solutions that connect to industrial field bus protocols such as BACnet, LON and Modbus, as well as IP-based protocols – especially when those solutions are enabled to work seamlessly togeth... » read more

Auto Power Becoming Much More Complex
By Bryon Moyer - 14 May, 2020 - Comments: 0

Rising electronics content in automobiles is putting increased focus on automotive power delivery networks (PDNs). Safety implications mean that thorough power design and verification, along with novel power isolation techniques, are needed at the vehicle level, involving both electrical and mechanical considerations. The electronic takeover can be measured by the percentage that electronic ... » read more

‘More Than Moore’ Reality Check
By Ann Mutschler - 14 May, 2020 - Comments: 1

The semiconductor industry is embracing multi-die packages as feature scaling hits the limits of physics, but how to get there with the least amount of pain and at the lowest cost is a work in progress. Gaps remain in tooling and methodologies, interconnect standards are still being developed, and there are so many implementations of packaging that the number of choices is often overwhelming. ... » read more

Using AI-Optimized Tuning To Design 5G And mmWave Filters
By David Shin - 14 May, 2020 - Comments: 0

The demand for 5G applications increases the need for radio frequency (RF) and microwave filter components in the mm-Wave frequency bands. The SynMatrix online interface with the AI-optimized tuning panel. “5G applications present some unique challenges to mm-Wave and 5G passive components,” said Diamond Liu, product manager of SynMatrix. “Fabrication capability limitations make i... » read more

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