Cloud Characterization
By WeiLii Tan - 19 Dec, 2019 - Comments: 0

Library characterization is a compute-intensive task that takes days to weeks to complete. Runtimes for library characterization are increasing due to larger library sizes, higher number of operating conditions to characterize, as well as the need for statistical variation modeling in libraries at 22/20nm and smaller process nodes. Cloud platforms offer a way to accelerate library characterizat... » read more

Will Open-Source Processors Cause A Verification Shift?
By Ann Mutschler - 19 Dec, 2019 - Comments: 0

While the promised flexibility of open source could have advantages and possibilities for processors and SoCs, where does the industry stand on verification approaches and methodologies from here? Single-source ISAs of the past relied on general industry verification technologies and methodologies, but open-source ISA-based processor users and adopters will need to review the verification flows... » read more

AI Chips Driving Need For New Test Implementation Methodologies
By David Buck - 19 Dec, 2019 - Comments: 0

Artificial intelligence has never been more in the news than it is today.  From picking stock market investments to autonomous driving, we have heard about what AI can do when it works and what happens when it goes awry. The consequences are huge if AI doesn’t work which puts a lot of pressure on hardware engineers to ensure that their chips can be extensively tested for proper and safe func... » read more

When Is Robustness Verification Complete?
By Janusz Kitel - 19 Dec, 2019 - Comments: 0

Understandably, hardware designed for an aircraft, or indeed any safety critical application, must be robust. I also believe that all engineers wish to verify their designs as thoroughly as possible, anyway. However, there are limiting factors; most notably the high complexity of most designs. Since we are unable to discover and verify the design against all abnormal conditions, the main questi... » read more

What Worked, What Didn’t In 2019
By Brian Bailey - 19 Dec, 2019 - Comments: 1

2019 has been a tough year for semiconductor companies from a revenue standpoint, especially for memory companies. On the other hand, the EDA industry has seen another robust growth year. A significant portion of this disparity can be attributed to the number of emerging technology areas for semiconductors, none of which has reached volume production yet. Some markets continue to struggle, a... » read more

Configurable, Easy-To-Use, Packaged Reliability Checks
By Mentor, a Siemens Business - 18 Dec, 2019 - Comments: 0

Using a packaged checks flow lets designers quickly select, configure and run custom reliability checks and check combinations to help design companies achieve today’s demanding time-to-market schedules while ensuring product reliability. To read more, click here. » read more

Verdi Transaction Debug Platform: A Simplified Way To Debug IIP Designs And SoC
By Synopsys - 18 Dec, 2019 - Comments: 0

Authors: Abhishek Upadhyay, R&D Engineer, Synopsys, and Kanak Rajput, Application Engineer, Synopsys Design problems that appear in the late phases of the development cycle can be extremely difficult to track down and debug, thus putting project schedules at risk. It’s not uncommon for an engineer to run the verification test on what appears to be the main design problem, only to find the ... » read more

Bricked IoT Devices Are Casualties Of Lax Semiconductor Security
By Ben Levine - 18 Dec, 2019 - Comments: 2

Earlier this summer, a new strain of destructive malware known as Silex began to spread and effectively brick unprotected IoT devices. Although victims of Silex theoretically can resurrect their IoT devices by manually reinstalling factory firmware, most remain wary of an installation process that is often time consuming and complicated. Moreover, many victims assume their device has suffered a... » read more

Kahn Process Network: Parallel Programming Without Races And Non-Determinism
By Silexica - 18 Dec, 2019 - Comments: 0

Modern personal computing devices feature multiple cores. This is not only true for desktops, laptops, tablets and smartphones, but also for small embedded devices like the Raspberry Pi. In order to exploit the computational power of those platforms, application programmers are forced to write their code in a parallel way. Most often, they use the threading approach. This means multiple parts o... » read more

Managing Power Dynamically
By Ann Mutschler - 18 Dec, 2019 - Comments: 1

Design teams are beginning to consider dynamic power management techniques as a way of pushing the limits on performance and low power, leveraging approaches that were sidelined in the past because they were considered too difficult to deploy. Dynamic voltage and frequency scaling (DVFS), in particular, has resurfaced as a useful approach. Originally intended to dynamically balance performan... » read more

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