Blog Review: Dec. 18
By Jesse Allen - 18 Dec, 2019 - Comments: 0

Lam Research's David Haynes finds that taking advances made at 300mm and applying them via upgrades to 200mm equipment is a cost appropriate strategy to quickly improve yield and add capacity. Synopsys' Taylor Armerding looks at which of this year's many data breaches hit corporate wallets the hardest and how the cost of privacy noncompliance is expected to rise with California's CCPA and st... » read more

Scaling, Packaging, And Partitioning
By Ed Sperling - 17 Dec, 2019 - Comments: 0

Prior to the finFET era, most chipmakers either focused on shrinking or packaging, but they rarely did both. Going forward, the two will be inseparable, and that will lead to big challenges with partitioning of data and processing. The key driver here, of course, is that device scaling no longer provides appreciable benefits in power, performance and cost. Nevertheless, scaling does provide ... » read more

Finding Defects In IC Packages
By Mark LaPedus - 17 Dec, 2019 - Comments: 0

Several equipment makers are ramping up new inspection equipment to address the growing defect challenges in IC packaging. At one time, finding defects in packaging was relatively straightforward. But as packaging becomes more complex, and as it is used in markets where reliability is critical, finding defects is both more difficult and more important. This has prompted the development of a ... » read more

New Packaging Roadmap
By Katherine Derbyshire - 17 Dec, 2019 - Comments: 3

Historically, the electronics industry has drawn sharp distinctions between the integrated circuit chip, the package that protects it from the environment, and the board that connects it to other devices in a complete system. The circuit and systems worlds have been largely isolated from each other, using different tools, different processes, and different metrics for success. While integrated ... » read more

Co-Design For The AI Era
By Buvna Ayyagari-Sangamalli - 17 Dec, 2019 - Comments: 0

Welcome to the second piece in our blog series examining how the computing industry can work in new ways to enable the AI Era. In our first blog, my colleague Ellie Yieh described the enormous opportunities and challenges facing the industry as we enter a new decade, and she offered a path for accelerating innovation—from materials to systems—based on a “New Playbook” for driving im... » read more

A Promising Future For Interconnect IP
By Rich Wawrzyniak - 17 Dec, 2019 - Comments: 0

Complexity of SoC designs continues to increase primarily due to increased demand for functionality and performance in all electronic devices. Studies that Semico Research has conducted on the SoC design landscape shows the number of discrete SIP blocks has continued to rise in response to increased market requirements from new applications and richer feature sets. Table 1: Comparison of 1st... » read more

Sandia’s Fab Gets An Upgrade
By Nishita Rao - 17 Dec, 2019 - Comments: 0

Sandia National Laboratories just finished updating equipment in its microelectronics fab, marking the completion of the first phase of a 3-year fab upgrade program. The transition from 6-inch to 8-inch wafer sizes will align the Department of Energy national lab with industry standards to ensure easier access to tools, spare parts and raw materials. Sandia is a prestigious member of the... » read more

What’s Next For High Bandwidth Memory
By Mark LaPedus - 17 Dec, 2019 - Comments: 1

A surge in data is driving the need for new IC package types with more and faster memory in high-end systems. But there are a multitude of challenges on the memory, packaging and other fronts. In systems, for example, data moves back and forth between the processor and DRAM, which is the main memory for most chips. But at times this exchange causes latency and power consumption, sometimes re... » read more

Manufacturing Bits: Dec. 16
By Mark LaPedus - 16 Dec, 2019 - Comments: 0

Imec-Leti alliance At the recent IEEE International Electron Devices Meeting (IEDM), Imec and Leti announced plans to collaborate in select areas. The two R&D organizations plan to collaborate in two areas—artificial intelligence (AI) and quantum computing. Imec and Leti have been separately working on AI technologies based on various next-generation memory architectures. Both entitie... » read more

N7 FinFET Self-Aligned Quadruple Patterning Modeling
By Coventor - 16 Dec, 2019 - Comments: 0

In this paper, we model fin pitch walk based on a process flow simulation using the Coventor SEMulator3D virtual platform. A taper angle of the fin core is introduced into the model to provide good agreement with silicon data. The impact on various Self-Aligned Quadruple Patterning process steps is assessed. Etch sensitivity to pattern density is reproduced in the model and provides insight on ... » read more

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