category: A Bit About Memory

category: Auto, Security & Edge AI

ADAS: MIPI Is Key
By Joseph Rodriguez - 10 Mar, 2022 - Comments: 0

Building on the enormous design and manufacturing base which made high-resolution, miniaturized digital cameras possible for mobile phones, the universe of MIPI applications has expanded to the automotive world. Today’s cars, particularly with the increasing sophistication of Advanced Driver Assistance Systems (ADAS), are brimming with cameras, sensors, and displays. Park assist, driver monit... » read more

It’s Official: HBM3 Dons The Crown Of Bandwidth King
By Frank Ferro - 10 Feb, 2022 - Comments: 0

With the publishing of the HBM3 update to the High Bandwidth Memory (HBM) standard, a new king of bandwidth is crowned. The torrid performance demands of advanced workloads, with AI/ML training leading the pack, drive the need for ever faster delivery of bits. Memory bandwidth is a critical enabler of computing performance, thus the need for the accelerated evolution of the standard with HBM3 r... » read more

Advancing Signaling Rates To 64 GT/s With PCI Express 6.0
By Tim Messegee - 13 Jan, 2022 - Comments: 0

From the introduction of PCI Express 3.0 (PCIe 3.0) in 2010 onward, each new generation of the standard has offered double the signaling rate of its predecessor. PCIe 3.0 saw a significant change to the protocol with the move from 8b/10b to highly efficient 128b/130b encoding. The PCIe 6.0 specification, now officially released, doubles the signaling rate to 64 gigatransfers per second (GT/s) a... » read more

Scaling DDR5 RDIMMs To 5600 MT/s
By John Eble - 09 Dec, 2021 - Comments: 0

Looking forward to 2022, the first of the DDR5-based servers will hit the market with RDIMMs running at 4800 megatransfers per second (MT/s). This is a 50% increase in data rate over top-end 3200 MT/s DDR4 RDIMMs in current high-performance servers. DDR5 memory incorporates a number of innovations, such as Decision Feedback Equalization (DFE), and a new DIMM architecture which enable that speed... » read more

MIPI On Wheels: Enabling ADAS Applications
By Joseph Rodriguez - 11 Nov, 2021 - Comments: 0

Formed in 2003, the Mobile Industry Processor Interface (MIPI) Alliance brought together leading system and chip companies to provide standards for the essential video interface technologies for cameras and displays in phones. Over the years, the alliance has expanded its scope to publish specifications covering physical layer, multimedia, chip-to-chip and inter-processor communications (IPC), ... » read more

Latency Considerations Of IDE Deployment On CXL Interconnects
By Paul Karazuba - 14 Oct, 2021 - Comments: 0

Certain applications and hardware types – emerging memory, artificial intelligence/machine learning (AI/ML), and cloud servers, to name a few – can realize significant performance advantages when a low latency interface is employed. However, traditional interconnects like PCI Express (PCIe) often do not offer low enough latencies required to optimize these applications. In response, the Com... » read more

On the Road To Higher Memory Bandwidth
By Frank Ferro - 09 Sep, 2021 - Comments: 0

In the decade since HBM was first announced, we’ve seen two-and-a-half generations of the standard come to market. HBM’s “wide and slow” architecture debuted first at a data rate of 1 gigabit per second (Gbps) running over a 1024-bit wide interface. The product of that data rate and that interface width provided a bandwidth of 128 gigabytes per second (GB/s). In 2016, HBM2 doubled the s... » read more

GDDR6 Memory On The Leading Edge
By Frank Ferro - 12 Aug, 2021 - Comments: 0

With the accelerating growth in data traffic, it is unsurprising that the number of hyperscale data centers keeps rocketing skyward. According to analysts at the Synergy Research Group, in nine months (Q2’20 to Q1’21), 84 new hyperscale data centers came online bringing the total worldwide to 625. Hyperscaler capex set a record $150B over the last four quarters eclipsing the $121B spent in ... » read more

CXL Signals A New Era Of Data Center Architecture
By Tim Messegee - 08 Jul, 2021 - Comments: 0

An exponential rise in data volume and traffic across the global internet infrastructure is motivating exploration of new architectures for the data center. Disaggregation and composability would move us beyond the classic architecture of the server as the unit of computing. By separating the functional components of compute, memory, storage and networking into pools, composed on-demand to matc... » read more

Accelerating AI/ML Inferencing With GDDR6 DRAM
By Frank Ferro - 10 Jun, 2021 - Comments: 0

The origins of graphics double data rate (GDDR) memory can be traced to the rise of 3D gaming on PCs and consoles. The first graphics processing units (GPU) packed single data rate (SDR) and double data rate (DDR) DRAM – the same solution used for CPU main memory. As gaming evolved, the demand for higher frame rates at ever higher resolutions drove the need for a graphics-workload specific me... » read more

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