Debug Is About To Get Really Interesting Again


One of the great unheralded chapters in the history of electronics design is debug. After all, where there have been designs, there have been bugs. And there was debug, engaged in an epic wrestling match with faults, bugs and errors to determine which would prevail. Think about system in the 1970s and '80s. A typical system would consist of a CPU, (EP)ROM, RAM, Peripherals (PIC, UART, DMA, T... » read more

Adapting Formal


With more pressure to make designs efficient — from a power perspective, as well as from an overall design view — finding what can be removed from a design is one step closer. As discussed in the article published today, “What Can Be Cut From A Design?” — sequential analysis, based on formal verification technology, is gaining traction. I specifically asked Mentor Graphics’ direc... » read more

Confidence In 7nm Designs Requires Multi-Variable, Multi-Scenario Analysis


As designs move toward 7-nanometer (nm) process nodes, engineering and production cost dramatically increases and the stake in getting the design right the first time becomes significantly higher than ever before. You are faced with the question, “how confident are you in your design analysis coverage?” Tighter noise margin, increasing power density, faster switching current and greater ... » read more

The Challenges Of Designing An HBM2 PHY


Originally targeted at the graphics industry, HBM continues to gain momentum in the server and networking markets as system designers work to move higher bandwidth closer to the CPU. Expanding DRAM capacity – which boosts overall system performance – allows data centers to maximize local DRAM storage for wide throughput. HBM DRAM architecture effectively increases system memory bandwidth... » read more

Real-Time Virtualization – How Hard Can It Be?


What’s the first association you make when you hear of virtualization? Server farms? ‘The cloud’? Most people don’t think of embedded systems - never mind hard real-time - yet these are areas where virtualization is now becoming commonplace. Markets such as industrial, automotive and medical—many of which also have requirements around functional safety for products like car braking... » read more

Finding The Unexpected In High Performance Designs


It was growing dark as I drove a winding road on Mt. Hood, deep in the American northwest forest. The firs were thick, creating a lot of shadows and making it tough to see things clearly. Then out of the corner of my eye, I swear I saw a 10-foot “man” covered with brown fur. It looked a lot like a Wookie. But everyone knows Wookies aren’t real. It had to be Bigfoot! I slammed on th... » read more

TSMC: 10nm To Be Greater Than 10% Of 2017 Wafer Revenue


TSMC’s financial results for the 4th Quarter of 2016 were released on January 11, 2017 (PST) and showed that year-over-year fourth quarter revenue increased 28.8% and simultaneously net income and diluted EPS both increased 37.6%.  In U.S. dollars, TSMC’s fourth quarter revenue was $8.25 billion. TSMC's CFO, Ms. Lora Ho, reported that 2016 was a good year for TSMC and that the company set ... » read more

What’s Missing In Deep Learning?


It is impossible today to be unaware of deep learning/machine learning/neural networks -- even if what it all entails is not even clear yet. Someone who is intimately familiar with this area, and has some thoughts on this is Chris Rowen, founder of Tensilica (now part of Cadence), who is now a self-described hat juggler. He is still active Cadence several days a month, working technically on... » read more

When DDR DRAM Is Right For Automotive Systems


Most of the processors contained within automobiles are relatively small and with modest memory requirements that can be served by SRAM and non-volatile memory. The type of computing, image processing, and graphics displays that are possible with a more powerful CPU connected to DRAM have largely been restricted to the non-safety-critical infotainment system in the vehicle – until now. Advanc... » read more

The Challenges Of Designing 28G And 56G SerDes IP


The industry move to 56 Gbps PAM4 is undoubtedly one of the greatest challenges currently facing SerDes IP designers and their customers. To begin with, shifting to 56 Gbps PAM4 immediately causes a loss of 9 dB. While the baud rate is 28 Gbaud, there are now three eyes stacked on top of each other. Nevertheless, there is still demand for 35+ dB reach. This is a significant challenge which requ... » read more

← Older posts Newer posts →