Micro-Architectural Exploration For Low Power Design


By Abhishek Ranjan, Saurabh Shrimal and Sanjiv Narayan In the first part of this series, we discussed the need to perform power optimizations and exploration at higher levels of abstractions, where the potential to reduce the power consumption was highest. While fine-grained local changes (like clock-gating, operand isolation, etc.) for power reduction are well understood and widely adopted,... » read more

The Power Of Software


There is no argument about the increasing importance of software in system designs today, given the intimate and integral role it plays in directing the very hardware it is co-designed with. There is also a very good case for certain kinds of software that lend themselves more to certain types of processors. This, of course, depends on what is meant by the type of processor, asserted Coli... » read more

Scalability From Granularity


You might have seen that ARM TechCon is happening this week in Silicon Valley, with a number of product announcements from the IP giant accompanying the conference. One of those is the A-35, which stuck out for me in terms of the range of scalability possible, among other things. Here is a graphic that shows the range of scalability: [caption id="attachment_23671" align="alignright" wid... » read more

Smaller, Faster, Cheaper


Sometimes the most intriguing market growth comes in “unsexy” applications. Take the mobile market for example. Overall growth rates are cooling, as you’d expect with a maturing market. But in 2020, 1 billion smart phones are expected to ship in the entry-level category. This implies an 8% compounded annual growth rate, making entry mobile the most rapidly expanding mobile market segme... » read more

System-Aware Full-Chip Power Integrity And Reliability


At the core of every electronics system is a chip that has to meet multiple conflicting requirements such as increased functionality, best power efficiency, highest reliability, lowest design cost and short design schedule. Meeting these requirements poses a major challenge, especially for systems on chip (SoCs) that are designed using advanced processes. Ensuring that the SoCs meet power an... » read more

Micro-Architectural Exploration For Low Power Design


By Abishek Ranjan, Saurabh Shrimal and Sanjiv Narayan The adoption of finFET technology has created a tectonic shift in the chip design landscape. In addition to better performance (within the same power envelope) and higher reliability, finFETs have significantly reduced the leakage power at smaller technology nodes. At the same time, the share of dynamic power dissipation continues to rise... » read more

Stop Getting Burned By Power Consumption Surprises


Very rarely these days do we get silicon back and find that we have missed our timing or test constraints by a significant margin. We have robust EDA tools, libraries and design methodologies in place to ensure that we can cleanly signoff against these constraints. However, we do continue to see too many unfortunate “surprises” in silicon related power (energy) consumption and thermal issue... » read more

Power Requires Holistic Perspective


With the move to smaller manufacturing nodes, power must be looked at from a holistic perspective. Instead of just optimizing a device or devising next generation power gating, power must be considered in the context of the whole system, Aveek Sarkar, vice president of product engineering and support at Ansys/Apache mentioned during a recent discussion about 5nm. In fact, he said, this c... » read more

Accurate Thermal Analysis, Including Thermal Coupling Of On-Chip Hot Interconnect


Driven by rapid advancement in mobile/server computing and automotive/communications, SoCs are experiencing a fast pace of functional integration along with technology scaling. Advanced low power techniques are widely used, while meeting higher performance requirements using a variety of packaging technologies. The Internet of Things (IoT) is further opening up new applications with connected d... » read more

Think In Blocks


It always seems to come back to LEGOs, doesn’t it? Earlier this year I wrote about Google Project Ara, the so-called “LEGO” smart phone architecture unveiled in April. Project Ara uses the MIPI Alliance UniPro and M-PHY protocols as the backbone for a modular electronics architecture inside a smart phone “endoskeleton.” Using electro-permanent magnets (they don’t need a perma... » read more

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