Fast, Focused Early-Stage Circuit Verification Can Get You To Signoff Faster

By Kesmat Shahin - 23 Feb, 2023 - Comments: 0

Designers everywhere know that with the increasing complexity of integrated circuits (ICs), meeting tapeout schedules has become increasingly difficult. While there are often many reasons for missing tapeouts, one critical component is the significant amount of time needed to run the signoff layout verification cycle, which contributes to overall signoff process duration. Much of this schedule ... » read more

Importance Of Qualifying IP Revisions

By Siddharth Ravikumar - 30 Jan, 2023 - Comments: 0

Design intellectual property (IP) is the fundamental building block of the modern system on chip (SoC). As the scale and complexity of SoCs increases, usage of design IP blocks also increases rapidly, as they enable modularization and re-use of design components. As a result, the usage of design IP has grown rapidly in the past decade. An IP data library consists of many views and formats, w... » read more

Ensuring ESD Protection Verification With Industry-Standard Checks

By Mark Tawfik - 21 Dec, 2022 - Comments: 0

Electronic design automation (EDA) verification of electrostatic discharge (ESD) protection is a complex task. Different integrated circuit (IC) design companies use different ESD protection approaches, different design flows, and different verification tools. To establish a consistent and comprehensive ESD EDA verification flow, the ESD Association (ESDA) provides recommended ESD compliance ch... » read more

Mastering FOWLP And 2.5D Design Is Easier Than You Think

By Bill Acito - 22 Nov, 2022 - Comments: 0

IC packaging has come into its own, where once traditional packaging was a “necessary evil,” today’s packaging can add significant value. There is an increase in functional density and flexibility by providing a platform for heterogeneous design assembly. Where designs implemented in an SoC can become too large to yield satisfactorily and too difficult to implement on one process node, pa... » read more

Considering The Power Of The Cloud For EDA

By Michael White - 27 Oct, 2022 - Comments: 0

By Michael White, Siemens EDA, in technical collaboration with Peeyush Tugnawat, Google Cloud, and Philip Steinke, AMD At DAC 2022, Google Cloud, AMD, and Calibre Design Solutions presented an EDA in the cloud solution that enables companies to access virtually unlimited compute resources when and as needed to optimize their design and verification flows. If your company is considering addin... » read more

Debug This! How To Simplify Coverage Analysis And Closure

By Yara Essam - 10 Oct, 2022 - Comments: 0

For years the process of ASIC and FPGA design and verification debug consisted primarily of comprehending the structure and source code of the design with waveforms showing activity over time, based on testbench stimulus. Today, functional verification is exponentially complex with the emergence of new layers of design requirements (beyond basic functionality) that did not exist years ago — f... » read more

Why Every Design IP Needs A Complete QA Methodology

By WeiLii Tan - 22 Sep, 2022 - Comments: 0

Design IP is a key contributor to innovation in the semiconductor industry today. As the complexity and scale of silicon designs increase, so does design and verification time. Design IP enables modularization and re-use of design components, so that designers can leverage already-existing components as a baseline to accelerate design schedules. Therefore, it is not surprising that the usage of... » read more

The Complex Art Of Handling S-Parameters

By Pradeep Thiagarajan - 12 Sep, 2022 - Comments: 1

By Pradeep Thiagarajan and Youssef Abdelkader IC design is transforming at an accelerated pace along with fabrication technology. The need to incorporate more functionality has led to denser dies, multi-die chips, stacked 3D ICs, and advanced packaging. Furthermore, the increasing demand for enhanced connectivity with more and faster access to data continues to drive technology towards highe... » read more

Earlier SoC Design Exploration And Verification Gets Better Designs To Tapeout Faster

By Nermeen Hossam - 25 Aug, 2022 - Comments: 0

By Nermeen Hossam and John Ferguson Between the complexity of advanced node design verification and the competition to be first to the market, system-on-chip (SoC) designers no longer have the luxury of waiting until each sub-block of a chip is DRC-clean to start their chip assembly and verification. Today’s SoC designers typically start chip integration in parallel with block development.... » read more

2.5/3D IC Reliability Verification Has Come A Long Way

By Dina Medhat - 01 Aug, 2022 - Comments: 0

2.5D/3D integrated circuits (ICs) have evolved into an innovative solution for many IC design and integration challenges. As shown in figure 1, 2.5D ICs have multiple dies placed side-by-side on a passive silicon interposer. The interposer is placed on a ball grid array (BGA) organic substrate. Micro-bumps attach each die to the interposer, and flip-chip (C4) bumps attach the interposer to the ... » read more

← Older posts Newer posts →

Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

NAND Flash Targets 1,000 Layers

New techniques go beyond improved deposition and etching, but challenges stack up, too.

by Bryon Moyer

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.