category: Test, Measurement and Analytics

category: IoT, Security & Automotive

Extremely Large Exposure Field With Fine Resolution Lithography Technology To Enable Next Generation Panel Level Advanced Packaging
By Onto Innovation - 07 Dec, 2021 - Comments: 0

The growing demand for heterogeneous integration is driven by the 5G market that includes smartphones, data centers, servers, HPC, AI and IoT applications. Next-generation packaging technologies require tighter overlay to accommodate a larger package size with finer pitch chip interconnects on large format flexible panels. Heterogeneous integration enables next-generation device performance ... » read more

Engineers’ Experiences Around The World
By Ben Tsai - 07 Dec, 2021 - Comments: 0

As CTO, I see my role partially as strengthening the engineering community through program reviews, engineering education programs, conferences, seminars, and the product life cycle process at KLA. I also think it is critically important to spark engineering enthusiasm – helping engineers rediscover the excitement and curiosity that helps drive innovation. When inspired to create, engineers c... » read more

Enablers And Barriers For Connecting Diverse Data
By Anne Meixner - 09 Nov, 2021 - Comments: 0

More data is being collected at every step of the manufacturing process, raising the possibility of combining data in new ways to solve engineering problems. But this is far from simple, and combining results is not always possible. The semiconductor industry’s thirst for data has created oceans of it from the manufacturing process. In addition, semiconductor designs large and small now ha... » read more

Reversible Chain Diagnosis
By Siemens EDA - 09 Nov, 2021 - Comments: 0

For advanced technologies, the industry is seeing very complicated silicon defect types and defect distribution. One consequence is that scan chain diagnosis becomes more difficult. To improve the resolution of scan chain diagnosis, Tessent Diagnosis can use new scan chain test patterns to leverage a reversible scan chain architecture. This paper describes the novel scan chain architecture t... » read more

More Errors, More Correction in Memories
By Bryon Moyer - 09 Nov, 2021 - Comments: 1

As memory bit cells of any type become smaller, bit error rates increase due to lower margins and process variation. This can be dealt with using error correction to account for and correct bit errors, but as more sophisticated error-correction codes (ECC) are used, it requires more silicon area, which in turn drives up the cost. Given this trend, the looming question is whether the cost of ... » read more

Coping With Parallel Test Site-to-Site Variation
By Anne Meixner - 09 Nov, 2021 - Comments: 1

Testing multiple devices in parallel using the same ATE results in reduced test time and lower costs, but it requires engineering finesse to make it so. Minimizing test measurement variation for each device under test (DUT) is a multi-physics problem, and it's one that is becoming more essential to resolve at each new process node and in multi-chip packages. It requires synchronization of el... » read more

Advanced Modeling In FTIR Offers New Applications For HVM
By Benoit Ravot - 09 Nov, 2021 - Comments: 0

In the leading high-volume manufacturing (HVM) process flows, materials-enabled scaling has increased inline applications for compositional metrology. A previous blog discussed how Fourier transform infrared (FTIR) spectroscopy was used for inline composition measurements. These measurements informed advanced process control for the wafer-level processing of selectively etched 3D NAND wordli... » read more

Novel Reversible Chain Diagnosis Improves Resolution
By Jayant D'Souza - 09 Nov, 2021 - Comments: 0

Yield ramp for ICs designed on advanced process technologies faces new challenges because of the very complicated silicon defect types and defect distribution. Yield ramp and yield improvement are not just about profitability and time-to-market, but also have a role in today’s electronics supply chain crisis. That means yield ramp affects not just the IC maker, but the global economy. Ever... » read more

Automotive Keyless Entry SoC Test Methodologies And Techniques
By Philip Brock - 09 Nov, 2021 - Comments: 0

By Philip Brock, Louis Benton, Jr., and Jonvyn Wongso Passive Entry Passive Start (PEPS) technology has become standard in the automotive market for keyless operation. A secure wireless communication system, PEPS enables you to lock and unlock the vehicle, and start and stop the vehicle without physically using the key. Electronic functionality embedded in the key fob to interact with the ve... » read more

Expanding Silicon Lifecycle Management To Real-Time System Performance Optimization
By Steve Pateras - 09 Nov, 2021 - Comments: 0

Semiconductor development is currently in one of its periodic crises, with many factors combining to require dramatically new technologies and methodologies. Chips continue to grow ever larger and more complex, with 3D IC devices adding another layer of challenges. Huge data centers, autonomous vehicles, and algorithms using artificial intelligence (AI) and machine learning (ML) drive a relentl... » read more

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