category: System-Level Design

category: IoT, Security & Automotive

Developing Robust Finite State Machines Code With Lint Tools
By Alex Gnusin - 26 Nov, 2019 - Comments: 0

As design size and complexity grows, the design verification effort grows even more. It takes significant amount of time to thoroughly verify complex control logic of a design, which is the key and the most critical component of design functionality. One of the most common design patterns in the control logic design are finite state machines. They could be designed in different styles, state an... » read more

Thoroughly Verifying Complex SoCs
By Ann Mutschler - 26 Nov, 2019 - Comments: 0

The number of things that can go wrong in complex SoCs targeted at leading-edge applications is staggering, and there is no indication that verifying these chips will function as expected is going to get any easier. Heterogeneous designs developed for leading-edge applications, such as 5G, IoT, automotive and AI, are now complex systems in their own right. But they also need to work in conju... » read more

A Reliable I/O Ring For A Reliable SoC
By Abdellah Bakhali - 26 Nov, 2019 - Comments: 0

What is an input/output (I/O) ring, and why should I care about it? If you’re a system-on-chip (SoC) designer, you had better know the answer to that question. SoCs are the darlings of the semiconductor industry—they combine all the typical functionality of a computer (central processing unit (CPU), memory, input/output (I/O) ports, and storage) on a single chip. They’re particularly popu... » read more

Optimizing Hardware Faster
By Ed Sperling - 26 Nov, 2019 - Comments: 0

Maximillian Odendahl, CEO of Silexica, sat down with Semiconductor Engineering to talk about high-level synthesis and the changing role of this technology. What follows are excerpts of that conversation. SE: What is the direction that high-level synthesis is heading in? Odendahl: The direction hasn’t changed, but in the past HLS was not usable by the software guys. The main push right n... » read more

Enhancing IO Ring Checks For Consistent, Customizable Verification
By Mentor, a Siemens Business - 25 Nov, 2019 - Comments: 0

The Calibre PERC IO ring checker framework eliminates manual checking by providing a robust DRC-like environment to verify all IO placement rules with sign-off quality. Running on the first LEF/DEF floorplan, the IO ring checker provides early and full coverage of IO ring placement rules, enabling changes with minimal impact on the layout. Fast, accurate debugging and correction ensures that So... » read more

Accelerating Financial Applications With SLX FPGA
By Silexica - 25 Nov, 2019 - Comments: 0

This white paper demonstrates how engineers creating FPGA-based hardware accelerators for financial market models can take advantage of SLX FPGA. SLX FPGA can be used to accelerate optimization efforts for financial market models targeting option pricing. In this paper, two implementations of computation intensive models for pricing options are discussed, namely the Black-Scholes and Heston pri... » read more

Using PCIe Real World Interface For High-Speed Hybrid Prototyping
By Synopsys - 25 Nov, 2019 - Comments: 0

This white paper highlights a novel approach to hybrid prototyping using a PCIe interface between the HAPS FPGA-based prototyping and the Virtualizer virtual prototyping. The use of PCIe real world interface helps to deliver a prototyping system, running fast enough to enable embedded software development and hardware-software co-validation in the shortest possible time. The hybrid prototyping ... » read more

Portable Stimulus And Digital Twins
By Brian Bailey - 25 Nov, 2019 - Comments: 0

It has been a year since Accellera's Portable Test and Stimulus Specification became a standard. Semiconductor Engineering sat down to discuss the impact it has had, and the future direction of it, with  Larry Melling, product management director for Cadence; Tom Fitzpatrick, strategic verification architect for Mentor, a Siemens Business; Tom Anderson, technical marketing consultant for OneSp... » read more

ISO 26262:2018 Fault Analysis In Safety Mechanisms
By OneSpin Solutions - 25 Nov, 2019 - Comments: 0

Authors: Jörg Grosse1, Mark Hampton1, Sergio Marchese1, Jörg Koch2, Neil Rattray1, Alin Zagardan2 1OneSpin Solutions, Munich, Germany 2Renesas Electronics Europe, Duesseldorf, Germany ISO 26262-5 requires the determination of hardware safety metrics, including SPFM and LFM. Latent and residual diagnostic coverage are also important metrics to assess the effectiveness of safety mechanisms... » read more

Week In Review: Design, Low Power
By Jesse Allen - 22 Nov, 2019 - Comments: 1

Accellera formed the Universal Verification Methodology Analog/Mixed-Signal Working Group (UVM-AMS WG), which will work to develop a standard that will provide a unified analog/mixed-signal verification methodology based on UVM to improve the verification of AMS integrated circuits and systems. “Our objective is to standardize a method to drive and monitor analog/mixed-signal nets within UVM,... » read more

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