category: System-Level Design

category: IoT, Security & Automotive

System Bits: Oct. 23
By Ann Mutschler - 23 Oct, 2018 - Comments: 0

Adapting machine learning for use in scientific research To better tailor machine learning for effective use in scientific research, the U.S. Department of Energy has awarded a collaborative grant to a group of researchers, including UC Santa Barbara mathematician Paul Atzberger, to establish a new data science research center. According to UCSB, the Physics-Informed Learning Machines for M... » read more

Week In Review: Design, Low Power
By Jesse Allen - 19 Oct, 2018 - Comments: 0

Arm announced its new roadmap promising 30% annual system performance gains on leading edge nodes through 2021. These gains are to come from a combination of microarchitecture design to hardware, software and tools. They are branding this new roadmap 'Neoverse.' The first delivery will be Ares – expected in early 2019 – for a 7nm IP platform targeting 5G networks and next-generation cloud t... » read more

Blog Review: Oct. 17
By Jesse Allen - 17 Oct, 2018 - Comments: 0

Arm's Shidhartha Das explores the challenges of power delivery in designing mobile systems and the importance of focusing on peak power consumption. Synopsys' Meenakshy Ramachandran explains the basics of Display Stream Compression and how it works to increase the effective bandwidth enabling support of high resolution displays. Cadence's Paul McLellan shares tips on more effective market... » read more

System Bits: Oct. 16
By Ann Mutschler - 16 Oct, 2018 - Comments: 0

Solving the quantum verification problem UC Berkeley doctoral candidate Urmila Mahadev spent 8 years in graduate school solving one of the most basic questions in quantum computation, which is how to know whether a quantum computer has done anything quantum at all, according to Quanta Magazine. In her paper, Mahadev presents the first protocol allowing a classical computer to interactively ... » read more

Week In Review: Design, Low Power
By Jesse Allen - 12 Oct, 2018 - Comments: 0

Deals AI startup Enflame (Suiyuan) Technology purchased multiple licenses of Arteris IP's FlexNoC interconnect IP for use as the on-chip communications backbone of its AI training chips for use in cloud datacenters. Enflame cited easy creation of regular topologies used in AI chips and the ability to take advantage of HBM2 memories. Phison, a maker of NAND flash controller ICs, inked�... » read more

Blog Review: Oct. 10
By Jesse Allen - 10 Oct, 2018 - Comments: 0

In a video, Cadence's Megha Daga dives into sparsity in neural networks and how it affects bandwidth, performance, and power efficiency. In a video, Mentor's Colin Walls takes a look at efficient embedded code, and why that means different things at different times. Synopsys' Eric Huang argues that in the realm of video standards, HDMI, DisplayPort, and USB Type-C are set to continue comp... » read more

System Bits: Oct. 9
By Ann Mutschler - 09 Oct, 2018 - Comments: 0

Sensing with light pulses In a development expected to be useful in applications including distance measurement, molecular fingerprinting and ultrafast sampling, EPFL researchers have found a way to implement an optical sensing system by using spatial multiplexing, a technique originally developed in optical-fiber communication, which produces three independent streams of ultrashort optical pu... » read more

So Many Waivers Hiding Issues
By Brian Bailey - 05 Oct, 2018 - Comments: 0

Semiconductor Engineering sat down to discuss problems associated with domain crossings with Alex Gnusin, design verification technologist for Aldec; Pete Hardee, director, product management for Cadence; Joe Hupcey, product manager and verification product technologist for Mentor, a Siemens Business; Sven Beyer, product manager design verification for OneSpin; and Godwin Maben, applications en... » read more

Week In Review: Design, Low Power
By Jesse Allen - 05 Oct, 2018 - Comments: 0

Mirabilis Design debuted an AI-driven tool for performance analysis and architecture exploration of SoCs and embedded systems. VisualSim AI Processor Generator creates pipeline-accurate models that have port integration with standard buses and memories, which is used to compare different processor families, optimize the specification and identify system bottlenecks. The generated model supports... » read more

Performance Benchmarking Embedded FPGAs
By Flex Logix - 03 Oct, 2018 - Comments: 0

When evaluating the performance of an embedded FPGA, one needs to evaluate the performance of each of the individual modules that make up an FPGA. The basic modules are: Reconfigurable logic building blocks (RBB-Logic), Fine-granularity logic containing LUTs, carry-forwarding adder chain, and flip-flops Reconfigurable DSP building blocks (RBB-DSP), Medium-granularity arith... » read more

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