A Configurable Test Infrastructure Using A Mixed-Language And Mixed-Level IP Integration IP-XACT Flow

By Arteris - 20 Dec, 2023 - Comments: 0

This paper written with NXP describes an efficient integration flow for mixed-language and mixed-abstraction level IPs through IP-XACT flow automation. Authors Erwin de Kock (NXP), Jos Verhaegh (NXP) and Serge Amougou (Arteris) describe: A configurable and reusable test infrastructure for RTL designs as an application of mixed-level and mixed-language integration using the IP-XACT stand... » read more

Blog Review: Dec. 20

By Jesse Allen - 20 Dec, 2023 - Comments: 0

Siemens' Huw Geddes finds that the flexibility offered by the RISC-V ISA can introduce further verification and validation requirements to ensure that the combination of extensions and customization not just works but does not break anything else while delivering expected performance, plus looks at how processor trace can help. Cadence's Gustavo Araujo explains the various optimizations in t... » read more

Blog Review: December 13

By Jesse Allen - 13 Dec, 2023 - Comments: 0

Synopsys' Charles Dittmer discusses key and emerging use cases for Bluetooth Low Energy and how combining BLE with other wireless protocols can open new avenues of functionality for application areas including automotive, hearables, and retail. Cadence's Neelabh Singh points out changes in the terminologies describing USB4 links and shows the various possible link configurations put forth by... » read more

Blog Review: Dec. 6

By Jesse Allen - 06 Dec, 2023 - Comments: 0

Cadence's Vinod Khera checks out potential implications of generative AI for EDA, including how it could increase the learning rate of students and reduce the rising verification cost. Synopsys' Kiran Vittal considers the driving factors behind RISC-V's growth and why it is becoming increasingly important for applications ranging from automotive to 5G mobile, AI, and data centers. Siemens... » read more

AI Accelerator Architectures Poised For Big Changes

By Ann Mutschler - 04 Dec, 2023 - Comments: 5

AI is driving a frenzy of activity in the chip world as companies across the semiconductor ecosystem race to include AI in their product lineup. The challenge now is how to make AI run faster, use less energy, and to be able to leverage it from the edge to the data center — particularly with the rollout of large language models. On the hardware side, there are two main approaches for accel... » read more

The Good Old Days Of EDA

By Brian Bailey - 30 Nov, 2023 - Comments: 5

Nostalgia is wonderful, but there is something about being involved in the formative years of an industry. Few people ever get to experience it, and it was probably one of the most fortuitous events to have happened in my life. Back in the early '80s, little in the way of design automation existed. There were a few gate- and transistor-level simulators, primarily for test and a few 'calculators... » read more

System State Challenges Widen

By Brian Bailey - 30 Nov, 2023 - Comments: 0

Knowing the state of a system is essential for many analysis and debug tasks, but it's becoming more difficult in heterogeneous systems that are crammed with an increasing array of features. There is a limit as to how many things engineers can keep track of, and the complexity of today's systems extends far beyond that. Hierarchy and abstraction are used to help focus on the important aspect... » read more

EDA Pushes Deeper Into AI

By Karen Heyman - 30 Nov, 2023 - Comments: 0

EDA vendors are ramping up the use of AI/ML in their tools to help chipmakers and systems companies differentiate their products. In some cases, that means using AI to design AI chips, where the number and breadth of features and potential problems is exploding. What remains to be seen is how well these AI-designed chips behave over time, and where exactly AI benefits design teams. And all o... » read more

3D-ICs May Be The Least-Cost Option

By Brian Bailey - 30 Nov, 2023 - Comments: 1

When 2.5D and 3D packaging were first conceived, the general consensus was that only the largest semiconductor houses would be able to afford them, but development costs are quickly coming under control. In some cases, these advanced packages actually may turn out to be the lowest-cost options. With stacked die [1], each die is considered to be a complete functional block or sub-system. In t... » read more

Nascent Chiplet Tech Gaining Attention In Defense and Commercial Industries

By Ben Miller - 30 Nov, 2023 - Comments: 0

The economic benefits derived from Moore's Law have changed, and not for the better. This shift – especially on the manufacturing side of system-on-chip (SoC) devices, has both the defense and commercial customers in the semiconductor industry wondering what will come next. One way to extend Moore's Law's cost, feature, and size benefits is with multi-chip technology, now commonly known as... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

New AI Processors Architectures Balance Speed With Efficiency

Hot Chips 24: Large language models ratchet up pressure for sustainable computing and heterogeneous integration; data management becomes key differentiator.