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Speeding Up Analog
By Ann Mutschler - 05 Aug, 2015 - Comments: 1

Semiconductor Engineering sat down to discuss analog design and how to speed up analog circuits with Kurt Shuler, vice president of marketing at Arteris; Bernard Murphy, CTO at Atrenta; Wilbur Luo, senior group director, product management for custom IC and PCB at Cadence; Brad Hoskins, director, IC design, microcontrollers at Freescale; and Jeff Miller, product manager at Tanner EDA. What foll... » read more

Speeding Up Analog
By Ann Mutschler - 16 Jul, 2015 - Comments: 0

Semiconductor Engineering sat down to discuss analog design and how to speed up analog circuits with Kurt Shuler, vice president of marketing at Arteris; Bernard Murphy, CTO at Atrenta; Wilbur Luo, senior group director, product management for custom IC and PCB at Cadence; Brad Hoskins, director, IC design, microcontrollers at Freescale; and Jeff Miller, product manager at Tanner EDA. What foll... » read more

Power Breaks Everything
By Ed Sperling - 15 Jul, 2015 - Comments: 2

The emphasis on lowering power in everything from wearable electronics to data centers is turning into a perfect storm for the semiconductor ecosystem. Existing methodologies need to be fixed, techniques need to be improved, and expectations need to be adjusted. And even then the problems won't go away. In the past, most issues involving power—notably current leakage, physical effects such... » read more

Moore Memory Problems
By Brian Bailey - 09 Jul, 2015 - Comments: 0

The six-transistor static memory cell (SRAM) has been the mainstay of on-chip memory for several decades and has stood the test of time. Today, many advanced SoCs have 50% of the chip area covered with these memories and so they are critical to continued scaling. “The SRAM being used in modern systems is similar to the SRAM they were using in the 1970s and 1980s,” says Duncan Bremner, ch... » read more

Divide And Conquer: A Power Verification Methodology Approach
By Ann Mutschler - 09 Jul, 2015 - Comments: 0

It’s no secret that the power verification challenge has grown by leaps and bounds in the recent past, especially considering design complexity and the sharp rise in the number of power domains in an SoC. As a result, SoC teams want to apply a rigorous [getkc id="10" kc_name="Verification"] flow, observed Gabriel Chidolue, verification technologist at [getentity id="22017" e_name="Mentor G... » read more

Speeding Up Analog
By Ann Mutschler - 09 Jul, 2015 - Comments: 0

Semiconductor Engineering sat down to discuss analog design and how to speed it up with Kurt Shuler, vice president of marketing at Arteris; Bernard Murphy, CTO at Atrenta; Wilbur Luo, senior group director, product management for custom IC and PCB at Cadence; Brad Hoskins, director, IC design, microcontrollers at Freescale; and Jeff Miller, product manager at Tanner EDA. What follows are excer... » read more

Cloud 2.0
By Ed Sperling - 09 Jul, 2015 - Comments: 0

Corporate data centers are reluctant adopters of new technology. There is too much at stake to make quick changes, which accounts for a number of failed semiconductor startups over the past decade with better ideas for more efficient processors, not to mention rapid consolidation in other areas. But as the amount of data increases, and the cost of processing that data decreases at a slower rate... » read more

Tale Of Two HLS Viewpoints
By Brian Bailey - 09 Jul, 2015 - Comments: 0

The Design Automation Conference attracts several co-located conferences, symposiums and other such gathering of people, often on more specialized topics than would appeal to the general DAC attendees. Some of them are more research-focused, but one conference is somewhat strange in that it is about a subject that has transitioned to commercial tool development and yet still remains an active a... » read more

IP Integration Challenges Increase
By Ed Sperling - 08 Jul, 2015 - Comments: 0

Semiconductor Engineering sat down with Chris Rowen, CTO of [getentity id="22032" e_name="Cadence"]'s IP group; Rob Aitken, an [getentity id="22186" comment="ARM"] fellow; Patrick Soheili, vice president of product management and corporate development at [getentity id="22242" e_name="eSilicon"]; Navraj Nandra, senior director of marketing for DesignWare analog and mixed-signal IP at [getentity ... » read more

IP Integration Challenges Increase
By Ed Sperling - 24 Jun, 2015 - Comments: 0

Semiconductor Engineering sat down with Chris Rowen, CTO of [getentity id="22032" e_name="Cadence"]'s IP group; Rob Aitken, an [getentity id="22186" comment="ARM"] fellow; Patrick Soheili, vice president of product management and corporate development at [getentity id="22242" e_name="eSilicon"]; Navraj Nandra, senior director of marketing for DesignWare analog and mixed-signal IP at [getentity ... » read more

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