category: Top Stories

category: Auto, Security & Edge AI

The Art Of LP Analog
By Ann Mutschler - 12 Feb, 2015 - Comments: 0

The best way to reduce power in analog chips is to make architectural changes or adopt a new architecture for the individual block. However, there are also some design techniques used to reduce power in analog circuitry. Unlike digital circuitry, which allows an engineer to leverage a low power library and optimize through a constraints file with the EDA software to reduce power, the same do... » read more

Emulation Uses Increase
By Ed Sperling - 12 Feb, 2015 - Comments: 0

For more than two decades, [getkc id="30" comment="emulation"] was a technology in search of a market. While on paper it has always made sense to speed up simulation, using hardware acceleration was so pricey that few companies could justify the cost. Fast-forward to today and emulation is a major contributor to the bottom line at all of the Big Three [getkc id="7" kc_name="EDA"] companies. ... » read more

With Responsibility Comes Power
By Brian Bailey - 12 Feb, 2015 - Comments: 0

The debate continues as to whether [getkc id="106" kc_name="power"] has risen to become a primary design consideration, or if it remains secondary to functionality and performance. What is indisputable is the rise in the importance of both power and energy conservation. As technology improves, additional aspects of the design flow are being affected. With that, the focus for power reduction is ... » read more

Power Management Verification Requires Holistic Approach
By Ann Mutschler - 12 Feb, 2015 - Comments: 0

Semiconductor Engineering sat down to discuss power management [getkc id="10" kc_name="Verification"] issues with Arvind Shanmugavel, senior director, applications engineering at [getentity id="22021" e_name="Ansys-Apache"]; Guillaume Boillet, technical marketing manager at [getentity id="22026" e_name="Atrenta"]; Adam Sherer, verification product management director at [getentity id="22032" e_... » read more

Reliability Definition Is Changing
By Ed Sperling - 12 Feb, 2015 - Comments: 0

Since the invention of the integrated circuit, reliability has been defined by how long a chip continues to work. It either turned on and did what it was designed to do, or it didn't. But that definition is no longer so black-and-white. Parts of an SoC, or even an IP or memory block, can continue to function while other parts do not. Some may work intermittently, or at lower speeds. Others may ... » read more

One-On-One: Walid Abu-Hadba
By Ed Sperling - 11 Feb, 2015 - Comments: 0

Walid Abu-Hadba, chief product officer at [getentity id="22021" e_name="Ansys"] (and a former top executive at Microsoft), sat down with Semiconductor Engineering to talk about systems engineering and why the starting point is no longer the SoC. What follows are excerpts of that conversation. SE: How do you define system? Abu-Hadba: It's everything. It's the entire product and where the p... » read more

Signal Integrity Issues
By Ed Sperling - 04 Feb, 2015 - Comments: 0

Semiconductor Engineering sat down to discuss signal integrity with Rob Aitken, research fellow at [getentity id="22186" comment="ARM"]; PV Srinivas, senior director of engineering for the Place & Route Division of [getentity id="22017" e_name="Mentor Graphics"]; and Bernard Murphy, chief technology officer at [getentity id="22026" e_name="Atrenta"]. What follows are excerpts of that conver... » read more

New Challenges For Wearables
By Ed Sperling - 26 Jan, 2015 - Comments: 1

The earliest recorded mention of a wristwatch dates back to the late 1500s, but it really began gaining adherents in Great Britain’s Boer War campaign as a way of synchronizing military actions beyond the line of sight. Strapping a pocket watch to a horse or a camel simply didn’t work, and pulling it out of a jacket pocket was not only inconvenient, it was dangerous. Advertised as a “c... » read more

Signal Integrity Issues
By Ed Sperling - 21 Jan, 2015 - Comments: 0

Semiconductor Engineering sat down to discuss signal integrity with Rob Aitken, research fellow at [getentity id="22186" comment="ARM"]; PV Srinivas, senior director of engineering for the Place & Route Division of [getentity id="22017" e_name="Mentor Graphics"]; and Bernard Murphy, chief technology officer at [getentity id="22026" e_name="Atrenta"]. What follows are excerpts of that conver... » read more

Higher Frequencies Mean More Memory
By Ann Mutschler - 16 Jan, 2015 - Comments: 0

As SoCs get more complex, whether due to higher frequencies or adding more functionality, there is a spillover effect on bandwidth, [getkc id="22" kc_name="memory"] and power. There is no simple way to just turn up the clock frequency in a complex [getkc id="81" kc_name="SoC"]. That relatively straightforward objective will likely require more power domains, more cores, more ways to move sig... » read more

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