category: Top Stories

category: IoT, Security & Automotive

To Bus Or Not To Bus, That Is The Question
By Ann Mutschler - 31 Jul, 2009 - Comments: 0

By Ann Steffora Mutschler When you hear the words, “block interface,” your ears may not perk up, but as system architects well understand, making the right choice between a bus or non-bus interface on an SoC is absolutely critical to design’s success in terms of power efficiency, reusability and performance. How many of the problems in new chip designs have to do with the interconne... » read more

ESL: Reality, Or A Pigment Of Your Fig Neuton?
By Various Writers - 31 Jul, 2009 - Comments: 0

By Clive "Max" Maxfield One of the questions I am often asked is: "Who's really using ESL tools such as modeling and are there any hiccups in the flow?" Another common question is: "What actually is ESL?" Perhaps we should address the latter question first. To some folks, ESL (electronic system level) means designing at a very high level of abstraction prior to making any hardware-softwar... » read more

Boost For Verification Methodologies
By Ed Sperling - 31 Jul, 2009 - Comments: 0

By Ed Sperling Synopsys introduced enhancements to its Verification Methodology Manual and Cadence began detailing new enhancements in its Open Verification Methodology. Both programs are in beta, yet they offer steps forward toward easing one of the biggest problem areas in chip development. With verification still consuming 70% or more of the non-recurring engineering costs of semicondu... » read more

The Argument For Low Power In The Data Center
By Ann Mutschler - 16 Jul, 2009 - Comments: 0

By Ann Steffora Mutschler For budgetary and ‘green’ motives, enterprise IT customers are demanding higher energy efficiency from their servers. This ultimately rests on the shoulders of the processor designer as the MPU is a significant source of power usage. Interestingly, the hidden and ugly truth is that for most data center managers, the cost of electricity for that data center is... » read more

Existing Circuit Styles Shed Light On Low-Power Design
By Cheryl Ajluni - 16 Jul, 2009 - Comments: 0

By Cheryl Ajluni Given the growing importance and impact of portable, battery-operated devices in today’s society, it’s easy to understand why power consumption has become such a critical factor in IC design. But it’s not just battery-operated devices that are driving the need for low-power design. In non-portable devices, the cost of providing power and the increased area resultin... » read more

First Down On The 40nm Line
By Ed Sperling - 30 Jun, 2009 - Comments: 0

The race to 40nm is over. Some chipmakers are already there, taping out designs and implementing IP that has already been qualified at the 40nm process. When exactly volume production begins and when yields improve is a matter of conjecture. TSMC so far is the only major foundry actively using the 40nm process, which is a half-node beyond 45nm. But the Common Platform already has briefed a... » read more

Making Quality A Top Priority in Next-Generation Designs
By Cheryl Ajluni - 25 Jun, 2009 - Comments: 0

By Cheryl Ajluni With system design such a complicated task these days, it is increasingly likely that designers will inadvertently overlook some details of the design process, or worse yet, simply not have the time to address them adequately. Time is readily spent focusing on things like performance, area, timing, and power, but what about something a bit more esoteric in nature—namely, qu... » read more

Custom IC Design: They Call This Progress?
By Ed Sperling - 25 Jun, 2009 - Comments: 0

By Ed Sperling For decades, analog and digital engineers have lived in completely separate worlds. The lines are blurring between those worlds, though, in complex SoCs. So far, the transition has been difficult, and most engineers predict it will get worse at future process nodes. The basic problem is that each world has functioned independently of the other from the start. They use different... » read more

The Impact of 3D Packaging
By Ann Mutschler - 11 Jun, 2009 - Comments: 0

With semiconductor packaging becoming a more crucial piece of the Moore’s Law roadmap, the industry is still sorting out the impact of a 3D design and packaging approach on design time, cost and power. 3D is now commonly used for high volume applications such as cell phones and SD cards, and is accomplished at the packaging step either through chip stacking or package-on-package (PoP) stac... » read more

Not A Household Name—Yet
By Various Writers - 11 Jun, 2009 - Comments: 0

By Alma Wang Spring and summer are typically the bustling seasons for China’s semiconductor industry. Each day, invitations arrive for members of the media to attend events, contests, and road shows. This year is different, though. It has been eerily quiet. And perhaps even stranger, a local IC design company that rarely makes media appearances announced a top-prize application design com... » read more

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