CMOS-Embedded STT-MRAM Arrays In 2xnm Nodes For GP-MCU Applications


Perpendicular Spin-Transfer Torque (STT) MRAM is a promising technology in terms of read/write speed, low power consumption and non-volatility, but there has not been a demonstration of high density manufacturability at small geometries. In this paper we present an unprecedented demonstration of a robust STT-MRAM technology designed in a 2x nm CMOS- embedded 40 Mb array. Key features are full a... » read more

High-Volume Manufacturing Device Overlay Process Control


By Honggoo Leea, Sangjun Hana, Jaeson Wooa, DongYoung Leea, ChangRock Songa, Hoyoung Heob, Irina Brinsterb, DongSub Choic, John C. Robinsonb aSK Hynix, 2091, Gyeongchung-daero, Bubal-eub, Icheon-si, Gyeonggi-do, 467-701, Korea bKLA-Tencor Corp., 8834 N. Capital of Texas Hwy, Austin, TX 78759 cKLA-Tencor Korea, Starplaza bldg.., 53 Metapolis-ro, Hwasung City, Gyeonggi-do, Korea Abstract ... » read more

Investigation Of The Influence of Controller Types On Room Thermal Behavior – A Simulation Study


To control the indoor temperature of rooms two kinds of approaches are common. The first one is to use standard PI-controllers with a set of default parameters, which often leads to insufficient performance, waste of energy and unacceptable comfort violations [Rahmati, 2003]. The other approach is to use specifically developed and adapted controllers [Seidel et al., 2015], which have the drawba... » read more

Disruption Is Here In Automotive And Ground Transportation: Are You Ready?


The automotive and ground transportation industry is being disrupted with the rise of shared, connected, self-driving, electrified vehicles. For those who can innovate fast, it is a once-in-a-century opportunity to leapfrog the competition and win the race to dominate the new mobility industry. Simulation is the key enabler. Are you ready for innovation through simulation? Engineering simula... » read more

Improving Test Coverage And Eliminating Test Escapes Using Analog Defect Analysis


While the analog and mixed-signal components are the leading source of test escapes that result in field failures, the lack of tools to analyze the test coverage during design has made it difficult for designers to address the issue. In this white paper, we explore the methodology for performing analog fault simulation of test coverage based on defect-oriented testing. In addition, we look at h... » read more

The Veloce Strato Platform: Unique Core Components Create High-Value Advantages


The Veloce Strato Emulation platform has sufficient execution speed, full visibility capabilities and ease-of-use in model creation and model updates to span the entire range of needs throughout the life of the design development process. To read more, click here. » read more

Sacrificial Laser Release Materials For RDL-First Fan-Out Packaging


The semiconductor industry is in a new age where device scaling will not continue to provide the cost reductions or performance improvements at a similar rate to past years when Moore’s law was the guiding principle for IC scaling. The cost of scaling below 7 nm nodes is rising substantially and requires significant investment in capital equipment and R&D spending for next-generation lithogra... » read more

Generating And Debugging Constraints For High-Speed Serial Instruments


This white paper addresses the specific need for designing constraints into your NI PXIe-6591R or PXIe-6592R High Speed Serial project. Constraints are an often overlooked requirement of the project and can take several weeks to analyze timing requirements on a design, implement constraints, and achieving successful compilations that pass timing. This guide will help reduce the amount of time s... » read more

Putting “Design” Back Into Design For Test In PCB Products


Design for manufacturing (DFM) has become a proactive part of the design process, but the same cannot be said for DFT. Whereas “left-shifting” DFM has reduced manufacturing problems, increased yield, reduced scrap levels, and simplified engineering rework, testability-related improvements have stayed flat during that same time. Unfortunately, as assembly costs have come down, and test-relat... » read more

designHUB: Design Reuse Made Real


It’s no secret: You can’t get to market quickly or efficiently without integrating and re-using IP technology in your system-on-chip (SoC) design. In the past 10 years alone, design re-use has doubled to the point where today you’ll find more than 150 reused blocks comprising 60-70% of the die area in an average SoC. The companies most successful with their IP-reuse strategies are thos... » read more

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