category: Whitepapers

category: IoT, Security & Automotive

The Value of Runtime Knowledge Management
By Applied Materials - 20 Sep, 2018 - Comments: 0

In clinical and commercial manufacturing when measures are taken to prevent deviations, the findings aren’t often shared across the enterprise and when corrective actions are taken to resolve an issue, they often don’t address the actual root cause(s). The Applied SmartFactory® Rx™ Knowledge Management solution allows knowledge captured in the R&D and design phases to be used th... » read more

Atomic Layer Etching: Rethinking the Art of Etch
By Lam Research - 20 Sep, 2018 - Comments: 0

Atomic layer etching (ALE) is the most advanced etching technique in production today. In this Perspective, we describe ALE in comparison to long-standing conventional etching techniques, relating it to the underlying principles behind the ancient art of etching. Once considered too slow, we show how leveraging plasma has made ALE a thousand times faster than earlier approaches. While Si is the... » read more

Advanced Defect Inspection Techniques For nFET And pFET Defectivity At 7nm Gate Poly Removal Process
By KLA-Tencor - 20 Sep, 2018 - Comments: 0

By Ian Tolle, GlobalFoundries, and Michael Daino, KLA-Tencor During 7nm gate poly removal process, polysilicon is removed exposing both NFET and PFET fins in preparation for high-k gate oxide. If the polysilicon etch is too aggressive or the source and drain are not sufficiently protected, the etch can damage the active region and render the FET inoperative. Different materials are used in t... » read more

Design Compliant Source Mask Optimization (SMO)
By PDF Solutions - 20 Sep, 2018 - Comments: 0

Source Mask Optimization (SMO) is required to extend the use of 193 water immersion lithography to the 22nm technology node. Although SMO is being aggressively pushed in volume production the layout design implications of this technology have not been openly discussed. In this paper, the impact of layout design style on simultaneous SMO of Logic and SRAM is studied. In particular the improvemen... » read more

Enabling Device Intelligence
By Synopsys - 18 Sep, 2018 - Comments: 0

The explosive growth in silicon and software for artificial intelligence applications is transforming everything we know about connectivity, energy-efficiency, mobility, and security. Machine learning (ML) techniques are already used in computer vision, object recognition, speech recognition, and big data analytics. Deep learning (DL) algorithms and neural networks are pushing both silicon and ... » read more

Chipping Away At Functional Safety Flaws In Automotive Electronics
By ANSYS - 17 Sep, 2018 - Comments: 0

Today’s automobiles are packed with electronics. From autonomous driving support and infotainment systems to mission-critical functions like braking, a car’s performance depends on the reliability of these electronics systems. While the semiconductors that lie at the heart of these systems have been not been a focus in the past, today their reliability is coming under closer scrutiny by bot... » read more

System-Level Test: Where Does It Fit?
By Astronics - 17 Sep, 2018 - Comments: 0

Our second C-Brief discusses where system-level test (SLT) best fits into your semiconductor test workflow. With automated testing equipment (ATE), a traditional workflow may consist of: Wafer sort (WS) Burn-in after packaging (BI) Combination of structural testing (ST) and functional testing (FT). As demands on high-volume manufacturing shift in response to wider industry and com... » read more

Accelerating SoC Time To Market With Cloud-Based Verification
By Cadence - 12 Sep, 2018 - Comments: 0

This paper discusses the growing use of cloud and hybrid cloud environments among semiconductor design and verification teams. The schedule and efficiency benefits seen by verification teams using cloud are specifically highlighted, due to the considerable compute requirements associated with verification of advanced node SoCs, and the significant impact verification has on the overall SoC proj... » read more

Low Power Coverage: The Missing Piece In Dynamic Simulation
By Mentor, a Siemens Business - 12 Sep, 2018 - Comments: 0

Through real design examples and case studies, this paper demonstrates how to achieve comprehensive low power design verification closure with all possible sources of power states, their transition coverage, and cross-coverage of power domains of interdependent states. As well the paper proposes a mechanism to combine and represent LP and non-LP coverage in a unified and adaptable database with... » read more

Low-Latency Image Acquisition And Processing With A Programmable Vision-System-On-Chip
By Fraunhofer EAS - 12 Sep, 2018 - Comments: 0

This work aims to demonstrate the benefits of using a Vision-System-on-Chip for image processing tasks with very high latency demands between image acquisition and processing. By leveraging a column-parallel, mixed-signal data path, which is entirely software-defined by three application-specific instruction- set processors (ASIPs), image data within multiple regions of interest can be analyzed... » read more

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