IC Compiler II: Finding The Best Floorplan, Fast

As designers strive to pack more and more functionality into todays’ SoC’s, design size (in terms of the number of transistors packed into a chip) is growing almost exponentially. This growth brings with it an unbounded increase in not just the technical complexity of performing the physical layout of the design due to capacity challenges, but also requires designers to make choices that ca... » read more

A Vision For Electronics Supply Chain Management

Supply chain disruptions and chip shortage have become household terms in recent times. COVID-19 highlighted the vulnerability of supply chains of countless industries and their critical role in the global economy. Companies across the electronics manufacturing value chain have been affected. At last count, the semiconductor shortage has already cost the automotive industry alone over $150 bill... » read more

Deep Learning (DL) Applications In Photomask To Wafer Semiconductor Manufacturing

How Advantest Corporation, ASML, Fraunhofer, imec, Siemens EDA and others are using deep learning in semiconductor manufacturing. Click here to read more. » read more

Review Of Virtual Wafer Process Modeling And Metrology For Advanced Technology Development

Semiconductor logic and memory technology development continues to push the limits of process complexity and cost, especially as the industry migrates to the 5 nm node and beyond. Optimization of the process flow and ultimately quantifying its physical and electrical properties are critical steps in yielding mature technology. The standard build, test, and wait model of technology development ... » read more

Unlocking PPA Benefits of Backside Routing

The power delivery network (PDN) is a critical part of any modern semiconductor device. Even with advanced power-saving technologies, today’s chips are hungry for power. Traditionally, power is distributed through metal layers on the same side of the substrate as the signal metal layers. This creates competition for the available layers and pushes the limits of fabrication technology to add m... » read more

Performance Boost In Powerful Real-Time Cortex-R Processor Using Data Prefetch Control

High-performance processors employ hardware data prefetching to reduce the negative performance impact of large main memory latencies. An effective prefetching mechanism can improve cache hit rate significantly. Data prefetching boosts the execution performance by fetching data before it is needed. While prefetching improves performance substantially on many programs, it can significantly red... » read more

Hybrid Methodology To Extract Kinetic And Magnetic Inductances For Superconductor Technologies

Integrated circuits (ICs) using superconductors have emerged as the technology of choice for artificial intelligence (AI), data centers, and cloud computing. However, innovative technology requires equally innovative physical verification solutions to ensure that these superconductor ICs deliver the performance and reliability they promise. We introduce an innovative hybrid methodology to extra... » read more

Low-Power Relaxation Oscillator With Temperature-Compensated Thyristor Decision Elements

This paper presents a low-power 140 kHz relaxation oscillator (ROSC) for low-frequency clock generators and timers. In voltage-mode ROSCs, unavoidable shunt current consumption results from voltage slewing at the integration capacitor. The proposed circuit employs CMOS thyristor-based decision elements which effectively reduce shunt currents by exploiting internal positive feedback. A complemen... » read more

PCI Express Test Overview

PCl Express, short for Peripheral Component Interconnect Express, is a high-performance and high-bandwidth serial communication interconnect standard. First proposed by Intel and further developed by the Peripheral Component Interconnect Special Interest Group (PCI-SIG) in replacement of bus-based communication architecture, such as PCI, PCI Extended (PCI-X), and Accelerated Graphics Port (AGP)... » read more

Quantum Well Design Basics

Key Takeaways The choice of materials for the quantum well and barrier layers is paramount. Materials must have compatible lattice structures to minimize defects, with common combinations including GaAs/AlGaAs, InGaAs/InP, and GaN/AlGaN. The width of the quantum well significantly influences the energy levels and density of states, where narrower wells result in greater separation betwe... » read more

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