category: Whitepapers

category: IoT, Security & Automotive

Unifying Storage Diversity: Leveraging PCIe IP for Multi-Device, Multi Form Factor Designs
By Synopsys - 24 Jul, 2024 - Comments: 0

In the fast-paced world of data storage, designers are racing to keep up with ever-evolving interface standards and form factors. This whitepaper explores the impact of these industry shifts, focusing on the integration of PCIe interfaces within the context of varying storage device form factors like the Enterprise and Datacenter Standard Form Factor (EDSFF). PCIe designs need to be flexible in... » read more

Essential Insights for Design PCIe 6.0 Interconnects
By Keysight - 24 Jul, 2024 - Comments: 0

PCI Express (PCIe) is a serial communication protocol that has progressed through generations to enhance data rates and functionality. The latest version, PCIe 6.0, doubles the data rate to 64 GT/s, enabling up to 256 GB/s of bandwidth in an x16 configuration. The technology incorporates PAM4 signaling and forward error correction to maintain high speeds with improved signal integrity and relia... » read more

CD Spec For Curvilinear Masks
By D2S - 23 Jul, 2024 - Comments: 0

Within the photomask industry, there's a major transformation from conventional Manhattan masks to more advanced curvilinear masks. Researchers from D2S and Micron Technology propose an equivalent CD spec for the curvy masks and use this spec to show that curvy masks have smaller mask variations than Manhattan masks. Find the technical paper here. Published June 2024. Linyong (Leo) Pang, ... » read more

Multi-tier Die Stacking Through Collective Die-to-Wafer Hybrid bonding
By Brewer Science - 23 Jul, 2024 - Comments: 0

A technical paper titled "Multi-tier Die Stacking Through Collective Die-to-Wafer Hybrid bonding" was published by researchers at imec, Brewer Science and SUSS MicroTec Lithography GmbH. Abstract "A collective die-to-wafer bonding flow is extended beyond the N=2 tier to the N=3 and N=4 tier by collectively bonding multiple layers of dies on top of a target wafer. The N=2 die-level is show... » read more

Rigid-Flex PCB Design Guidelines
By Siemens EDA - 17 Jul, 2024 - Comments: 0

This white paper is designed to guide you through the intricacies of rigid-flex printed circuit board (PCB) design. In today's electronics industry, there has never been more demand for compact, efficient, and versatile PCBs. Rigid-flex technology has emerged as a game-changer, offering engineers the flexibility to design boards that can bend and flex without sacrificing performance or reliabil... » read more

Evolving Edge Computing
By Arm - 17 Jul, 2024 - Comments: 0

Edge computing is a term that has been in use for a long time. Throughout the industry, there are many references to edge and many pre-conceptions about what that might mean. The term ‘edge’ is typically used for devices that exist on the edge of a network and can cover a plethora of use cases, ranging from the router in your house, a smart video camera surveying a parking lot, to a control... » read more

Speed AND Accuracy: First-Of-Its-Kind Broad-Spectrum CFD Solver Built Natively on GPUs
By Ansys - 17 Jul, 2024 - Comments: 0

Since the advent of computational methods to solve physics problems, especially in the realm of fluid dynamics, scientists and engineers have had to balance the need for accurate simulations with faster times to solution — with available computing resources affecting this balance. Now, we introduce to you a new broad-spectrum native GPU solver created by developers at Ansys. Find more i... » read more

Cadence Janus NoC System IP
By Cadence - 17 Jul, 2024 - Comments: 0

The Cadence Janus Network on Chip (NoC) is a new highly configurable soft IP designed to speed up the system-on-chip (SoC) and full system design cycle by reducing some of the problems associated with large SoCs. With many more processing nodes, as well as memory and I/O nodes designed into the SoC, the interconnect becomes a major design hurdle. Wiring congestion and wire loads introduce ch... » read more

Effective Monitoring, Test, and Repair of Multi-Die Designs
By Synopsys - 09 Jul, 2024 - Comments: 0

Despite clear advantages, there are numerous new challenges that need to be addressed for successful multi-die realization. The multi-die test challenges include: Bare chiplet level (pre-bond) Probe, dedicated/functional pads for test Test, diagnosis, and repair Interconnects (mid/post-bond) Die-to-die test access Lane test, diagnosis, and repair Multi-die ... » read more

Testing PAs under Digital Predistortion and Dynamic Power Supply Conditions
By NI - 09 Jul, 2024 - Comments: 0

The power amplifier (PA) – as either a discrete component or part of an integrated front end module (FEM) – is one of the most integral RF integrated circuits (RFICs) in the modern radio. In this application note, you will learn different techniques for testing PAs through an interactive application note with multiple how-to videos. To address these linearity and efficiency requirements,... » read more

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