A Survey Of Machine Learning Applications In Functional Verification


Functional verification is computationally and data-intensive by nature, making it a natural target of machine learning applications. This paper provides a comprehensive and up-to-date analysis of FV problems addressable by ML. Among the various ML techniques and algorithms, several emerging ones have demonstrated outstanding potential in FV. Yet despite the promising research results, criti... » read more

Achieving ISO/SAE21434 Cyber Security Using Secure Flash


ISO/SAE21434 specifies the requirements for making a car system more robust against cyber-attacks. It outlines the criteria during the concept, development, production, usage and decommission of automotive systems. The requirements of ISO 21434 applies to systems, subsystems and components whose development started after the publication of the standard in August 2021. ISO21434 has been made ... » read more

Solving the AppSec Puzzle: Connecting AppSec To Your DevOps Pipeline


Integrating application security (AppSec) into your software development life cycle and DevOps pipeline is increasingly important in today’s development environment. Commonly referred to as “shifting left” or “shifting everywhere,” AppSec integration helps avoid the late-stage testing and development that can delay product releases or lead to overlooked risks being promoted into produ... » read more

RT-600 Root Of Trust Series: A New Generation of Security Anchored In Hardware


This latest generation of the Rambus RT-600 Root of Trust IP offers many new features designed to support the security needs of customers today and into the future. These features include Quantum Safe Cryptography, Caliptra Root of Trust for Measurement (RoTM) emulation, an embedded physical unclonable function (PUF), as well as many architectural improvements, such as larger memory space and 6... » read more

HW/SW Security Mechanisms For Future Automotive Society


The demand of information security for automotive has substantially increased in recent years. The In-vehicle network is digitalized, and its connectivity is becoming very popular. Similar to the typical network security developed with the internet around 2000, the strong demand of cybersecurity within automotive is rapidly changing. Automotive hacking and theft caused by the flaw of security m... » read more

Placement And CTS Techniques For High-Performance Computing Designs


This paper discusses the challenges of designing high-performance computing (HPC) integrated circuits (ICs) to achieve maximum performance. The design process for HPC ICs has become more complex with each new process technology, requiring new architectures and transistors. We highlight how the Siemens Aprisa digital implementation solution can solve placement and clock tree challenges in HPC de... » read more

How To Boost ATE Power Supply Throughput


The test engineer’s job is not an easy one. There is constant pressure to improve system throughput. This white paper will guide you on how to increase throughput to reduce costs. Increased throughput comes from faster programming and command processing times, built-in output sequencing, and arbitrary waveform capabilities. Faster testing speeds will enable more rigorous testing of devices, d... » read more

The Road Ahead For SoCs In Self-Driving Vehicles


Automakers have relied on a human driver behind the wheel for more than a century. With Level 3 systems in place, the road ahead leads to full autonomy and Level 5 self-driving. However, it’s going to be a long climb. Much of the technology that got the industry to Level 3 will not scale in all the needed dimensions — performance, memory usage, interconnect, chip area, and power consumption... » read more

Synchronous Die-to-Die Signaling Using Aeonic Connect


This paper presents a system providing accurate clock alignment for on-die and die-to-die synchronous circuits. A low-frequency reference clock provides an accurate timing reference with low power consumption, while distributed delay lines align the endpoints of loosely constrained clock trees. For on-die clocks, this synchronization strategy severs the traditional relationship between power an... » read more

Calibre DesignEnhancer Design-Stage Layout Modification Improves Power Management Faster And Earlier


The faster a design can progress from implementation to signoff verification, the better the chances are of meeting tapeout schedules. The Calibre DesignEnhancer platform offers P&R and custom/analog design teams a fast, integrated environment for implementing Calibre-clean design modifications to reduce IR drop and EM and prepare for physical verification. Not only can designers reduce EM and ... » read more

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