category: Whitepapers

category: IoT, Security & Automotive

Radix Coverage For Hardware Common Weakness Enumeration (CWE) Guide
By Tortuga Logic - 03 Feb, 2021 - Comments: 0

MITRE's hardware Common Weakness Enumeration (CWE) database aggregates hardware weaknesses that are the root causes of vulnerabilities in deployed parts. A complete list can be found on the MITRE Hardware Design Webpage. Hardware CWEs are ideal to be used alongside internally developed security requirements databases and have been developed and submitted by both government and commercial design... » read more

10 Things You Ought To Know Before You Benchmark Your Software Security Program
By Synopsys - 03 Feb, 2021 - Comments: 0

Benchmarking can help you get a new software security initiative off the ground or better navigate an existing one. It is different from other measurement techniques because it focuses on excellence, includes detailed comparisons, and pools confidential information among numerous organizations. To get you started in the right direction, we’ve put together some quick tips so you get the mos... » read more

Hot Or Not? An Introduction To Electrical Thermal Co-Design
By Cadence - 03 Feb, 2021 - Comments: 0

Heat transfer is not a one-way street. Traditionally, thermal analysis and management is thought of as a mechanical problem. However, modern electronic products are highly susceptible to electronic thermal issues. The electronics are often both the cause of thermal issues and the victim of overheating if temperature profiles exceed specifications. Indeed, over 50% of IC failures are related ... » read more

Streaming Scan Network
By Siemens EDA - 27 Jan, 2021 - Comments: 0

The increasing complexity in large System on Chip (SoC) designs present challenges to design-for-test (DFT). Hierarchical DFT alleviates some of those challenges, by itself, is no longer enough. Adding Tessent Streaming Scan Network (SSN) technology eliminates the difficult and costly trade-offs between test implementation effort and manufacturing test cost by decoupling core-level and chip-lev... » read more

5G NR Design eMBB
By Cadence - 27 Jan, 2021 - Comments: 0

Next-generation 5G/6G communication systems will provide massive connectivity to the internet with extreme capacity, coverage, reliability, and ultra-low latency, enabling a wide range of new services made possible through innovative technologies. Enhanced mobile broadband (eMBB) extends the current mobile experience with high data throughput on the order of more than 10Gbps, high system capaci... » read more

An Automated Pre-Silicon IP Trustworthiness Assessment For Hardware Assurance
By OneSpin Solutions - 27 Jan, 2021 - Comments: 0

Paper presented by Sergio Marchese & John Hallman of OneSpin Solutions & The Aerospace Corporation. Integrated circuit designs include in-house and third-party intellectual properties that could contain hardware Trojans. An independent, trusted, and complete IP model, suitable for automated formal comparison with the IP register-transfer level (RTL) code using commercially available ... » read more

A Triple-Deck CFET Structure With An Integrated SRAM Cell For The 2nm Technology Node And Beyond
By Coventor - 20 Jan, 2021 - Comments: 0

A novel triple-deck CFET structure is proposed for the first time as a candidate for area scaling. The proposed triple-deck CFET aggressively stacks a pass gate over an inverter to form a half SRAM bit cell. The integration flow and full metal connectivity have been carefully designed for functionality and array assembly. Most of the pitch used in the process is around 40nm, which is patternabl... » read more

An Integrated Approach To Power Domain And Clock Domain Crossing Verification
By Siemens EDA - 13 Jan, 2021 - Comments: 0

Reducing power consumption is essential for both mobile and data center applications. The challenge is to lower power while minimally impacting performance. The solution has been to partition designs into multiple power domains which allow selectively reducing voltage levels or powering off partitions. Traditional low power verification validates only the functional correctness of power control... » read more

Realize A More Productive EDA Environment From HPE With AMD
By Ansys - 13 Jan, 2021 - Comments: 0

Few industries are more competitive than modern electronics manufacturing and chip design. Consumers expect devices to be faster, cheaper, and more reliable with each generation. Whether large or small, electronics manufacturers rely on electronic design automation (EDA) to enable these improvements. Click here to access the white paper. » read more

Machine Learning — Everywhere: Enabling Self-Optimizing Design Platforms for Better End-to-End Results
By Synopsys - 13 Jan, 2021 - Comments: 0

Machine-learning offers opportunities to enable self-optimizing design tools. Very much like self-driving cars that observe real-world interactions to improve their responses in different (local) driving conditions, AI-enhanced tools are able to learn and improve in (local) design environments after deployment. These new, ML-driven capabilities can be embedded in different design engines, gi... » read more

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