category: Whitepapers

category: IoT, Security & Automotive

A RISC-V ISA Extension For Ultra-Low Power IoT Wireless Signal Processing
By Codasip - 24 Mar, 2021 - Comments: 0

This work presents an instruction-set extension to the open-source RISC-V ISA (RV32IM) dedicated to ultra-low power (ULP) software-defined wireless IoT transceivers. The custom instructions are tailored to the needs of 8/16/32-bit integer complex arithmetic typically required by quadrature modulations. The proposed extension occupies only 2 major opcodes and most instructions are designed to co... » read more

Overcoming Next-Generation AESA Radar Design Challenges
By Cadence - 24 Mar, 2021 - Comments: 0

Phased array antennas were first used in military radar systems to scan the radar beam quickly across the sky to detect planes and missiles. These systems are becoming popular for a variety of applications and new active electronically scanned arrays (AESAs) are being used for radar systems in satellites and unmanned aerial vehicles. As these systems are deployed in new and novel ways, size and... » read more

Accelerate Custom Layout Using Custom Compiler’s User-Defined Device (UDD)
By Synopsys - 24 Mar, 2021 - Comments: 0

In this 7th video of the series, Kai Wang, Director of Engineering at Synopsys, discusses in-design electrical analysis, and why it is critical to use signoff engines to check and fix resistance, capacitance and electromigration issues during layout. Click here to access this video whitepaper. » read more

SVT: Six Stacked Vertical Transistors
By Coventor - 17 Mar, 2021 - Comments: 0

This paper presents a new design architecture for advanced logic SRAM cells using six vertical transistors (with carrier transport along the Z direction), stacked one on top of each other. Virtual fabrication technology was used to identify different process integration schemes to enable the fabrication of this architecture with a competitive XY footprint at an advanced logic node: a unit cell ... » read more

Defect Mitigation And Characterization In Silicon Hardmask Materials
By Brewer Science - 17 Mar, 2021 - Comments: 0

From SPIE Digital Library: In this study, metal contaminants, liquid particle count and on-wafer defects of Si- HMs and filtration removal rates are monitored to determine the effect of filter type, pore size, media morphology, and cleanliness on filtration performance. 5-nm PTFE NTD2 filter having proprietary surface treatment used in this study shows lowest defect count. Authors: Vineet... » read more

Chip Board Interaction Analysis Of 22nm FD-SOI Technology In WLP
By Amkor - 17 Mar, 2021 - Comments: 0

Recently, Wafer Level Packaging (WLP) has been in high demand, especially in mobile device applications as a path to enable miniaturization while maintaining good electrical performance. The relatively inexpensive package cost and simplified supply chain are encouraging other industries to adapt WLP capabilities for radio frequency (RF), communications/sensing (mmWave) and automotive applicatio... » read more

Deep Learning (DL) Applications In Photomask To Wafer Semiconductor Manufacturing
By eBeam Initiative - 17 Mar, 2021 - Comments: 0

The Survey: 2021 Deep Learning Applications List by eBeam Initiative members is a list of current deep learning efforts that are being used in photomask to wafer semiconductor manufacturing. Examples come from ASML, D2S, Fraunhofer IPMS, Hitachi High-Tech Corporation, imec, Siemens Industries Software, Inc., Siemens EDA, STMicroelectronics, and TASMIT. Published by the eBeam Initiative Membe... » read more

Nine Effective Features Of NVMe Verification IP For PCIe-Based SSD Storage
By Siemens EDA - 10 Mar, 2021 - Comments: 0

Non-Volatile Memory Express (NVMe) is a new software interface optimized for PCIe Solid State Drives (SSD). This paper provides an overview of the NVMe specification and examines some of its key features. We will discuss its pros and cons, compare it to other conventional technologies, and point out key areas to focus on during its verification. You will learn how NVMe Questa Verification IP... » read more

Designing ASIPs With Confidence
By Synopsys - 10 Mar, 2021 - Comments: 0

Well-designed ASIPs with a strong SDK combine C/C++ programmability with the power and performance of dedicated hardware. Product families based on ASIP platforms are often highly flexible, capable of addressing multiple market segments with the same silicon and handling updates in the field. They lean well towards software-driven verification with few penalties for late product requirement cha... » read more

Multiband Active Antenna Tuner For Cellular IoT Applications
By Cadence - 10 Mar, 2021 - Comments: 0

This white paper discusses related design challenges and solutions for developing a multiband active antenna tuner for cellular internet of things (IoT) massive machine-type communications (mMTC) applications. Click here to read more. » read more

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