Executive Briefing: Formal Attire


Kathryn Kranen, CEO of Jasper Design Automation, talks with Low Power-High-Performance Engineering about formal verification, where the pain points are in SoC design, and why there is still life left in Moore's Law. [youtube vid=x4jlo6_RRqw] » read more

Tech Talk: FinFETs, FD-SOI And The Future Of SoC Design


Mary Ann White, marketing manager for Synopsys' Galaxy Implementation Platform, talks with Low-Power/High-Performance Engineering about new opportunities to reduce power and improve performance, and where the pain points will be. [youtube vid=kuJdcHIRxfU] » read more

RTL Signoff


Piyush Sancheti, Atrenta's vice president of product marketing, talks with Low-Power/High-Performance Engineering about where the pain points are in design and why RTL signoff has become so important. [youtube vid=8Ra1_VmzW50] » read more

Roundtable: Is The Chip Ready


Mobile devices demand complex chips—so complex to build that signoff has become something of a balancing act between what the verification teams believe is good enough and time-to market demands. Low-Power/High-Performance Engineering talked about this with Simbal Rafiq, director of engineering at Applied Micro; Robert Hoogenstryd, senior director of marketing for design analysis and signoff ... » read more

Tech Talk: Getting To The Next Node


IBM's Gary Patton talks with Low-Power/High-Performance Engineering about finFETs, EUV, and the challenges of staying on the Moore's Law road map. [youtube vid=jtz9XSXyBp0] » read more

Roundtable: Battery Life Vs. Delay


Low-Power High-Performance Engineering talks about the challenges of dealing with latency in semiconductor design with Andrew Caples of Mentor Graphics, Chris Rowen of Tensilica, Drew Wingard of Sonics and Larry Hudepohl of MIPS Technologies. [youtube vid=Q_opQ3W9esA] » read more

Tech Talk: LP Design And Verification


Cadence's Qi Wang talks with Low-Power/High-Performance Engineering about power formats and what else can be done to save power in SoCs. [youtube vid=afJ6VQ0AYgg] » read more

Roundtable: Lower-Power Chips


Low Power-High Performance Engineering talks about problems in low-power design with Richard Trihy of GlobalFoundries, Leah Clark of Broadcom, Qi Wang of Cadence and Venki Venkatesh of Atrenta. [youtube vid=cD560pgEegk] » read more

Power Budgets: Where Is The Low-Hanging Fruit?


Low-Power Engineering looks for the best ways to cut power for a reasonable cost with Mentor Graphics, Synopsys, Apache Design Solutions, Oasys Design Systems and Xilinx. [youtube vid=Gqoenm00Mso] » read more

Moore’s Legacy


Low-Power High-Performance Engineering talks with MIPS' Mark Throndson, product marketing director, and Ranganathan "Suds" Sudhakar, chief architect, about Moore's Law, multicore chips, software, coherency and the insatiable global demand for speed. [youtube vid=VfvfYSkPpcs] » read more

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