Challenges Mount In Inspection And Metrology

Chipmakers are moving full speed ahead toward smaller process nodes, thereby driving up the costs and complexities in chip manufacturing. The migrations also are putting enormous stress on nearly all points of the fab flow, including a critical but unsung part of the business—process control.

Process control involves 20 or so different segments in the inspection and metrology arena. Generally, inspection searches for irregularities and defects on the wafer, while metrology involves the measurements of the chip structures themselves.

Inspection and metrology are becoming more difficult and costly at each node. Dealing with leading-edge planar devices is hard enough, but now chipmakers must contend with new chip architectures, such as 3D NAND, finFETs and stacked die. Adding to the complexity is the migration toward new materials.

All told, chipmakers face a dizzying array of challenges in process control, but two problems stand out in the crowd—defect inspection and 3D metrology. For example, the ability to detect sub-30nm defects is challenging with today’s inspection tools. And on another front, finFETs require 3D metrology to measure the structures, but the production tools generally don’t exist today. So, chipmakers must use the current methods, which can be a cumbersome and expensive process.

“I really think defect inspection is the hardest problem right now,” said Michael Lercel, senior director of nanodefectivity and metrology at Sematech. “There is also no lack of difficulties in metrology. Clearly, we are seeing an increase in the types of materials being used. That’s leading to more types of defects. And the overall cost (for process control) is becoming enormous.”

Needless to say, the inability to measure chip structures and find killer defects could lead to product delays and poor yields. “A one- or two-quarter delay can literally mean billions of dollars in lost opportunity costs going forward,” Lercel said. To solve the problem, the industry requires a new class of process control tools. Still to be seen, however, is when these systems will appear in the market and who will foot the R&D bill.

Wanted: New breakthroughs
Simply put, there is an urgent need for new breakthroughs in process control, particularly in defect inspection. “Killer defects are getting smaller, as the critical dimensions of chip features shrink with each node,” said Weston Twigg, an analyst with Pacific Crest Securities. “At the same time, throughput for inspection tools is slowing as the tools work to find the smaller defects. We believe throughput has fallen to one to two wafers per hour in some cases for a full-wafer inspection.”

In a fab, there are three basic types of wafer inspection tool technologies—brightfield, darkfield and e-beam. In the inspection flow, chipmakers first use e-beam inspection, mainly for engineering analysis. E-beam is able to find the smallest defects, but the throughputs are too slow to put these tools into the production flow.

Darkfield and brightfield inspection are optical technologies. Used in the backend, darkfield inspection is the measurement of light reflected at a lower angle. Brightfield inspection is the workhorse production tool in the fab. Used to find defects during the transistor fabrication in the front-end, brightfield collects light reflected from a defect. In turn, the defect appears dark against a white background.

Brightfield was supposed to run out of gas years ago, but vendors continue to extend the technology. “Still, it is getting more difficult to find defects using optical inspection tools, even with advanced brightfield inspection platforms from KLA-Tencor and Applied Materials,” Twigg said. “Inspection pixel size is 50nm to 100nm, yet customers are looking at defects in the 14nm range. Algorithms and sensors can help extend optical inspection, but it is becoming very challenging. Expect extensions to work for a few more nodes, but then expect a gradual shift of some steps to e-beam inspection.”

Still, the question is when will brightfield inspection finally hit the wall. Today’s brightfield tools are detecting defects as small as 10nm. “It’s been pretty amazing what the equipment suppliers have been able to do in terms of imaging capabilities,” Sematech’s Lercel said. “You can make compromises with this tool. It’s a question of when the compromises start to exceed the usable information. We are probably closer to that than we think.”

For the foreseeable future, however, the industry will continue to use brightfield, as there is no immediate successor for this technology. “What’s the replacement for brightfield? And what will the yields look like at the 10nm node? You can use e-beam inspection,” Lercel said. “E-beam inspection, with large dimensions, may be able to catch the problems. But you are probably going to miss some things. And if you miss some things, you are probably going to catch them as a yield loss days or weeks later, which is not efficient.”

For some time, the industry has been looking at one futuristic successor to brightfield—multi-beam e-beam inspection. Using multiple beams, multi-beam inspection enables the same fine resolutions as single e-beam inspection, but multi-beam provides faster throughputs. Today, however, there are no multi-beam inspection systems in the market. The technology requires millions of dollars to develop, but even then it could be several years before these machines are ready for prime time.

“At Sematech, we’ve been looking at (multi-beam inspection),” Lercel said. “It needs a lot of engineering. And if you really use it as a brightfield replacement, we are not talking about going from one beam to 10 beams. We are talking about going to thousands of beams. It’s much like multi-beam lithography, where you typically have thousands or tens of thousands of beams.”

Searching for 3D metrology
Besides defect inspection, there are other gaps in process control. One noticeable gap is metrology tools for complex structures such as 3D NAND and finFETs. For example, chipmakers would like to have a single metrology tool that can measure and characterize the individual structures in finFETs, such as the gate, fin height and the sidewall angles.

Current metrology tools are capable of handling planar devices, but they fall short in terms of providing these measurements for finFETs. “When we look at finFETs, we want to measure everything that we typically would have measured on a normal 2D CMOS device,” said John Allgair, senior member of the technical staff at GlobalFoundries. “From a user perspective, I would like to have a complete picture of what it is I am measuring in 3D. That’s ultimately what we want to know. We are still a long way from that.”

On top of that, there are new materials entering the picture for finFETs. “Precise control of the materials is needed to deliver the required structures,” said Adam Brand, director of the Transistor Technology Group at Applied Materials, at a recent event. “For fin formation, we need precision etch to allow the gate length to scale. We also need to scale the fin profile and STI fill. We also need to have lower-k materials for the spacer and etch stop layers. We also need to scale the high-k and metal-gate.”

Another technology, 3D NAND, has similar challenges. The successor to planar NAND, 3D NAND stacks vertical layers on top of each other. The good news is that 3D NAND doesn’t require aggressive and expensive lithography. “The downside from a metrology perspective is that it is really, really hard,” said Chris Bishop, R&D metrology manager at Micron.

“Today, a lot of the solutions just don’t exist,” Bishop said. “There are at least five different problems in respect to metrology. You have to be able to not only measure bulk as deposited inside a PVD chamber, but you have to keep control on each discrete layer deposition. You have to measure the CDs on the top and bottom as well as the recess at each tier. And all of that has to come together to create a structural composite model for what the profiles look like. It’s an incredibly difficult problem from an in-line perspective.”

Suppliers of 3D NAND and finFETs tend to use a combination of metrology tools. The workhorse tool is the scanning electron microscope (CD-SEM), which measures the critical dimensions in chip structures. “CD-SEMs have a tendency to be kind of slow and expensive and not always reliable,” Bishop said.

Another metrology technology, optical scatterometry (OCD), analyzes changes in the intensity of light in a device. “A lot of the work we’re doing is using scatterometry,” he said. “The metrology guys love it and hate it. It’s great technology, but there are a lot of complexities that go into building the models.”

In the future, what chipmakers want is a single metrology tool that can provide imaging and data in three dimensions. There are some futuristic candidates on the table. For example, a possible successor to the CD-SEM is a helium-ion microscope. And X-ray scattering (CD-SAXS) could succeed OCD.

The helium-ion microscope provides 3D imaging, but the technology has some serious drawbacks. “Ions are harder to deal with,” said Sematech’s Lercel. “The other concern with a helium-ion microscope is does it add more damage to a device?”

Like helium-ion microscopy, CD-SAXS is still in its infancy. “We are starting to look at CD-SAX,” Lercel said. “The question is how do you take a synchrotron-based X-ray technique in R&D and put it in a fab.”

All told, the industry will continue to use CD-SEMs, OCD and other current metrology technologies for the foreseeable future. But sooner or later, the industry will require some new breakthroughs. “We need an improved X-ray technology. We need to have advanced characterization systems in our labs,” said Micron’s Bishop. “We are faced with the possibility that technology is being gated by our ability to measure. That’s a very scary place to be.”