Chip Industry Technical Paper Roundup: Apr. 1

Nvidia GPUs; HW ANNs; optimizing GPU efficiency in LLMs; ONN with ReRAM crossbar array; GaN-on-diamond; DRAM read disturbance; chiplets co-optimization; ultra-low-leakage MCU for energy harvesting; testing FOWLP interconnects.

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New technical papers recently added to Semiconductor Engineering’s library:

Technical Paper Research Organizations
Analyzing Modern NVIDIA GPU cores Universitat Politècnica de Catalunya
Synaptic and neural behaviours in a standard silicon transistor KAUST and National University of Singapore
Mind the Memory Gap: Unveiling GPU Bottlenecks in Large-Batch LLM Inference Barcelona Supercomputing Center, Universitat Politecnica de Catalunya, and IBM Research
Hardware Implementation of Ring Oscillator Networks Coupled by BEOL Integrated ReRAM for Associative Memory Tasks IBM Research Europe and Eindhoven University of Technology
Thermal Boundary Resistance Reduction by Interfacial Nanopatterning for GaN-on-Diamond Electronics Applications University of Bristol, Cardiff University and Akash Systems
Revisiting DRAM Read Disturbance: Identifying Inconsistencies Between Experimental Characterization and Device-Level Studies ETH Zurich
CATCH: a Cost Analysis Tool for Co-optimization of chiplet-based Heterogeneous systems UCLA, Duke University and Arizona State University
Defect Analysis and Built-In-Self-Test for Chiplet Interconnects in Fan-out Wafer-Level Packaging Arizona State University
An Ultra-Low-Leakage Microcontroller with Configurable Power Management for Energy Harvesting IoT Devices Eindhoven University of Technology and Innatera Nanosystems

Find more semiconductor research papers here.



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