Chiplet to chiplet communication; SRAM scaling with monolithic 3D integration of 2D FETs; scan instrumentation for post-silicon test; photonic HW optimized for GenAI; GAA with source/drain metal contacts; optimizing GPU power consumption; Josephson junctions in quantum.
New technical papers recently added to Semiconductor Engineering’s library:
| Name of Paper | Research Organizations |
|---|---|
| Enhancing Test Efficiency through Automated ATPG-Aware Lightweight Scan Instrumentation | University of Florida |
| What Is Next for LLMs? Next-Generation AI Computing Hardware Using Photonic Chips | Chinese Univ. of Hong Kong, National University of Singapore, Univ. of Illinois Urbana-Champaign and UC Berkeley |
| Enabling static random-access memory cell scaling with monolithic 3D integration of 2D field-effect transistors | Pennsylvania State University |
| Modeling Chiplet-to-Chiplet (C2C) Communication for Chiplet-based Co-Design | Peter Grünberg Institute and Jülich Supercomputing Centre |
| Electrical Characteristics of ML and BL MoS2 GAA NS FETs With Source/Drain Metal Contacts” | National Yang Ming Chiao Tung University |
| Power Consumption Optimization of GPU Server With Offline Reinforcement Learning | KAIST and KT Research and Development Center |
| Josephson Junctions in the Age of Quantum Discovery | Lawrence Berkeley National Laboratory, UC Berkeley, Gwangju Institute of Science and Technology, Korea University, Max Planck and Anyon Computing |
Find more semiconductor research papers here.
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