3D and heterogeneous system integration research including capillary self-assembly of tiny dies with a size of less than 0.1 mm & advanced FHE using FOWLP.
T. Fukushima, “Chiplet-Based Advanced Packaging Technology from 3D/TSV to FOWLP/FHE,” 2021 Symposium on VLSI Circuits, 2021, pp. 1-2, doi: 10.23919/VLSICircuits52068.2021.9492335.
Abstract:
“More recently, “chiplets” are expected for further scaling the performance of LSI systems. However, system integration with the chiplets is not a new methodology. The basic concept dates back well over a few decades. The symbolic configuration of this concept based on the chiplets is 3D integration with TSV we have worked on since 1989. This paper introduces our 3D and heterogeneous system integration research from its historical activities to the latest efforts, including capillary self-assembly of tiny dies with a size of less than 0.1 mm and advanced flexible hybrid electronics (FHE) using fan-out wafer-level packaging (FOWLP).”
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