Emphasis on time to market and design costs is raising visibility for this approach.
Discussion about chiplets is growing as the cost of developing chips at 10/7nm and beyond passes well beyond the capabilities of many chipmakers.
Estimates for developing 5nm chips (the equivalent 3nm for TSMC and Samsung) are well into the hundreds of millions of dollars just for the NRE costs alone. Masks costs will be in the double-digit millions of dollars even with EUV. And that’s assuming that IP will be available for the most advanced nodes, which isn’t a sure thing because a number of IP vendors are debating which nodes to support and from which foundries.
This doesn’t mean that billions of 5/3nm chips won’t be produced and sold. Digital logic still benefits from scaling, and density increases generally mean faster processing, even if that density comes from more than one processing element. But analog circuitry does not benefit from scaling, and a planar SoC is becoming too expensive to continue scaling. Its successor is likely to be some sort of advanced package, with a mix of components developed at different process nodes and connected by some high-speed interconnect, whether that is a bridge, an interposer, TSVs, or even wirebonds. So rather than a 3nm SoC, it’s highly likely that a 3nm processor platform will be included inside a package.
This is where chiplets begin to look much more interesting. If IP can be hardened at the node that makes the most sense—which in the case of analog may be 250nm or 40nm, depending upon the IP—then IP blocks or subsystems can be fully characterized to the point where they can be used in multiple designs, almost like off-the-shelf components. That’s a much more attractive business model for IP vendors, because they can develop IP once and sell it for years to come to more customers in more market segments, and it levels the playing field for chipmakers around the globe.
Marvell and Kandou Bus were the first to jump on this shift. They announced a deal in 2016 under which Marvell would use Kandou’s chip-to-chip interconnect technology to tie multiple chips together. Since then, DARPA has established a chiplet program, and other companies say privately they are working on similar approaches.
The chiplet approach always has made sense from a conceptual level. Building chips from components such as standard memories, SerDes blocks, I/O and even processor logic should be relatively quick and much less expensive. That isn’t true today, mainly because there is no standardized way to make this all work. But the shift to advanced packaging is already in full swing, and that will only continue to gain steam at each new node. It takes too much power and time to drive signals across a large die, in which wires are scaled to the latest node and where contention for resources creates floorplanning and timing nightmares.
While the biggest chipmakers will continue to leverage density improvements at new nodes, they also are being forced to change direction in order to improve performance and lower power consumption. Intel’s EMIB and Samsung’s RDL bridge are indications of these shifts. So are the growth of fan-outs, systems in package, 2.5D, and a number of other packaging variants. There are more packaging options available today than ever before. Not all of them will survive, but the direction is at least clear. Advanced packaging is here to stay.
The next step is to reduce the cost and development time for advanced packaging, while also improving the predictability of these different packaging options. This is where the chiplet approach begins to look particularly interesting. How the marketplace for hardened IP will evolve, and who will run it, are unknown at this point. But the fact that more companies are discussing this option, and looking at how to harden IP into modules or chips, is the latest indication that change is on the way.
The chiplet approach is one of a number of options on the table, but it’s certainly an interesting one. And if it lives up to its promise, it could have significant implications for the entire chip industry.
Related Stories
Getting Serious About Chiplets
Issues involving known good die and test still remain, but this approach is getting a lot of interest.
Chiplets Gaining Steam
Hard IP could reduce time and cost for heterogeneous designs, but there are still challenges to solve.
The Chiplet Option
More companies are assessing pre-built and pre-verified circuits as a way of reducing time to market.
DARPA CHIPS Program Pushes For Chiplets
The U.S. government takes its own approach to heterogenous integration.
The Week In Review: Manufacturing
Making chiplets
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Maybe it’s the wrong way to simplify it like this. You got the broader context, this is one stage in the transition toward monolithic 3D. The roadmap and resource allocation should consider that long-term transition. If you don’t invest now, will be harder to catch up. Maybe it’s notable that TSMC has introduced wafer to wafer and, hopefully, that offering evolves quickly toward multi-tier FEOL.
The jury is still out about whether monolithic 3D will win. The general consensus a couple years ago was that 2.1/2.5D were transition packaging approaches on the road to 3D, while fan-outs were low-end packaging options. That’s not true anymore, and it’s not clear that monolithic 3D as it was first conceived–especially logic on logic–will be successful because there’s no easy way to get the heat out. The high-end solution with the most promise appears to be 2.5D, and chiplets will work quite well with that approach as well as fan-outs, systems-in-package, and multiple other packaging approaches.
Agree! The Xilinx’s New ACAP architecture & NOC give a novel definition and approach for chiplets.
Those kind of verdicts are missing the forest by focusing on the short term and usually come from execs and sales people. All this is part of an evolution. As the contact pitch evolves it enables more possibilities, doesn’t mean that exiting offerings will fade away, there will simply be more options. Due to wiring density, heat will be less of an issue than what people tend to assume, but there are other complications.
Monolithic 3D is already taking shape, horizontal GAA with logic and 3D NAND are paving the way. Ofc the holy grail is monolithic 3D that greatly reduces cost per transistor, if manufactured more like 3D NAND, but don’t know if anyone has any great ideas on how to do that. There are some ideas.
Longer term, some would argue that the future is neuromorphic, which has to be 3D and can’t be CMOS. IMEC has that slide with 3D-SIC, 3D-SOC, 3D-IC, look at it as a whole, an evolution, not individual commercial offerings. We move forward, new solutions are enabled and that’s great.
A winner, if something offers a lot more than everything else, that’s a winner. Anything on the roadmap with such potential? Used to be horizontal scaling, vertical comes next.