Foundries Expand Planar Efforts

Competition is heating up in the leading-edge foundry business, as vendors begin to ramp up their new 16nm/14nm finFET processes.

But that’s not the only action in the foundry arena. They are also expanding their efforts in the leading-edge planar market by rolling out new 28nm and 22nm processes.

On one front, TSMC is offering new 28nm variants, based on bulk CMOS technology. And on another front, Samsung is stepping up its activities with 28nm fully depleted silicon-on-insulator (FD-SOI) technology. And GlobalFoundries is readying a 22nm FD-SOI planar technology.

The foundries are developing new planar processes, and for good reason. There is still a sizeable foundry customer base that will never move to finFET processes at 16nm/14nm and beyond. Many others may eventually move to finFETs, but they are delaying their migrations due to cost and other factors.

In either case, many foundry customers will stay at 28nm and other planar nodes for longer than anticipated. “28nm is a popular node and it should last for at least five more years or longer,” said Samuel Wang, an analyst with Gartner. “It’s the last generation of planar technology that offers various speed and power options. And wafer prices are continuously coming down, as more foundry suppliers are offering 28nm.”

Going forward, many chipmakers are developing a new wave of leading-edge planar chips for a range of emerging applications, such as wearables and the (IoT). Automotive, wireless and other applications are also hot.

As before, chipmakers want to devise new planar chips with a noticeable bump in performance at lower power. But foundry customers face a multitude of difficult, if not confusing, technology options.

So, what are the new leading-edge planar options on the table? And what’s the best process path to follow?

Options galore
Basically, there are two types of technologies in the leading-edge planar market—bulk CMOS and FD-SOI. In the bulk CMOS camp, there are three main leading-edge planar process categories—plain-vanilla 28nm; 28nm variants; and 20nm.

TSMC, for one, is offering two new 28nm variants. One low-power version, dubbed 28ULP, is being positioned against 28nm FD-SOI. “[28ULP] is optimized for wearable applications,” said B.J. Woo, vice present of business development at TSMC.

FD-SOI is another viable technology option. This makes use of an ultra-thin insulating layer. This buried oxide layer is placed over the base silicon. Then, a very thin silicon film is situated in the transistor channel. All told, there is no need to dope the channel, thus making the transistor fully depleted.

FinFET is also a fully depleted technology. “FinFET is one way to do it. The other way of doing fully depleted is FD-SOI. FD-SOI consists of planar transistors that have very low-power attributes for IoT-type applications. Aside from that, the advantage of FD-SOI is body biasing. So if you use body biasing in your design, you can capitalize on the potential of the wide ranging power-performance attributes of FD-SOI,” said Kelvin Low, senior director of foundry marketing at Samsung.

“Compared to other variants of 28nm, the cost factor and the ability to use a much lower power supply and the flexibility of the body biasing are very important. FD-SOI offers the lowest power and the lowest leakage at the right cost point,” Low said.

Today, Samsung is offering a 28nm FD-SOI process. In addition, GlobalFoundries is working on a 22nm FD-SOI technology. “We view 22nm FD-SOI as a great cost/performance play, where you get finFET-type performance at 22nm and at 28nm cost,” said Thomas Caulfield, senior vice president and general manager of Fab 8 at GlobalFoundries.

So what’s the best solution? Is it bulk CMOS or FD-SOI? Or is it planar or finFETs? “The use of which technology should depend on the apps,” said Ronnie Vasishta, president and chief executive of eASIC, a fabless supplier of FPGAs and ASICs. “It’s not just power, performance and area, but also IP availability, expected yield improvements over time, and benefits of die size.

“The case for finFETs needs to be clear for each application,” Vasishta said. “For a full custom product like a microprocessor, it may be clear. However, the wafer costs will be higher due to lithography. The mask costs will be higher. The EDA tool costs could be much higher. And if the metal delays and fin variations are not accounted for correctly in standard ASIC design flows, then the performance benefit may not be as large as you may have wanted.”

There are other considerations. “The biggest challenge is power density,” said Ali Khakifirooz, a senior member of the technical staff at Cypress Semiconductor. “For years, CMOS scaling lived with a scaling of the device width at the same rate as the device pitch. Active power density was kept constant and active power at constant performance was scaled down by about 30% to 35% per node. FinFET broke this trend by keeping the device width constant or even allowing it to increase node to node. This is being advertised as a good thing, but if not managed, it will simply translate to higher power density. People have started complaining at 16nm/14nm, and I can imagine they will see a bigger problem at 10nm.”

More tradeoffs
So what are foundry customers thinking about these days? As it turns out, each customer has a different set of design, process and capacity requirements.

And not all of the action involves finFETs. For example, Ambarella, a fast-growing supplier of HD video compression and image processing chips, is shipping devices at 28nm and above. Ambarella makes chips for drones, sports cameras and security cameras. The company’s foundry partner is Samsung.

Clearly, planar chips are suitable for the booming action camera market. “We estimate Ambarella will ship SoCs into roughly 400,000 drones next quarter alone,” said Brad Erickson, an analyst with Pacific Crest Securities, in a recent report. “Pretty impressive for a market that we think did roughly a half a million units total all last year.”

In the drone market, OEMs are demanding. “They want to make units that are smaller and cheaper for the consumer,” said Jeff Campbell, senior product marketing manager at Ambarella. “The important thing for the drone guys is to have flying cameras with good resolution. They need 4K resolution. Right now, they are at 30 frames per second. They want to go to 60 frames per second.”

To keep up with the requirements, Ambarella must develop faster chips at lower power. “Thermally, it’s very challenging to build a product like this. If we can push our technology to the latest process node, that helps us get the power down,” Campbell said.

Ambarella’s latest device is based on 28nm technology. It is also exploring its options beyond planar, including finFETs.

Other foundry customers also provide high-performance chips, but many aren’t ready to jump on the finFET bandwagon, at least in the near term. For example, eASIC develops devices for the communications, storage and other segments. The company’s foundry partners include GlobalFoundries for 45nm bulk processes and TSMC for 28nm bulk.

“We are not doing finFETs yet,” eASIC’s Vasishta said. “We see 28nm having a very long life in the industry. The cost structure will remain competitive for a long time to come. That is why you are seeing multiple versions of 28nm optimized for different parameters.”

As a result of the plethora of options, foundry customers face some challenges in terms of selecting the right process and foundry vendor. “The challenge is that the foundries keep changing their roadmaps and offering variations. So, it is sometimes difficult to match the application to the required process technology when another one comes out six months later and then your competitor uses that technology, because their product development cycle is different,” Vasishta said.

Going forward, eASIC is exploring various process options for its next-generation chips. It is looking at FD-SOI and finFETs, but it has ruled out 20nm planar. “Not sure that planar 20nm really makes sense as a true node, as the performance gain is minimal and the power consumption is high due to the leakage,” he said.

“FD-SOI or other depleted channel technologies have some benefits when it comes to power, performance and pricing. (FD-SOI) solves some problems without having to go to finFETs,” he said. “The challenge with FD-SOI is the ecosystem for IP. The ability to scale to smaller geometries needs to be proven. We keep watching that space.”

As before, there is a perception that the SOI ecosystem is immature. In addition, SOI wafer costs are higher compared to bulk CMOS. And only a few chipmakers have adopted the technology, namely IBM and STMicroelectronics.

The tide may be turning, however. For example, Cisco, Ciena and Freescale have announced plans to adopt FD-SOI.
Regarding the technology issues, 28nm FD-SOI has fewer process steps compared to 28nm bulk. Fewer process steps offset the higher SOI substrate cost. “Expensive is relative. What are you comparing it to? There’s a wrong perception that FD-SOI is expensive because of the substrate cost. The substrate cost is higher, but how much you spend on a chip is also a function of skill,” Samsung’s Low said.

There are other positive developments. “We are starting to see a lot of healthy activity on the (FD-SOI) ecosystem side,” Low said. “On the design ecosystem side, Cadence and Synopsys have broadened what they are doing in terms of IP and EDA support.”

And in a separate move to help the design community, CEA Leti recently launched a new platform that enables chipmakers to reduce their product cycle times for FD-SOI and other technologies. The program, dubbed Silicon Impulse, consists of CEA-Leti, STMicroelectronics, Dolphin, CMP, Mentor Graphics, Cortus and Presto Engineering.

The Silicon Impulse program provides IC design services, IP and test. The program will also provide multi-project wafer (MPW) shuttles. The first 28nm FD-SOI shuttle is planned for February of 2016. It will take place at STMicroelectronics’ fab in Crolles.