How Long Will FinFETs Last?

Semiconductor Engineering sat down to discuss how long FinFETs will last and where we will we go next with Vassilios Gerousis, Distinguished Engineer at Cadence; Juan Rey, Sr. Director of Engineering for Calibre R&D at Mentor Graphics; Kelvin Low, Senior Director Foundry Marketing at Samsung; and Victor Moroz, Synopsys Scientist. What follows are excerpts of that conversation.

SE: What is the point at which FinFET runs out of steam?

Low: I think what’s clear at least is 14 and 10nm. That is really going from 14 obviously in mass production, 10 going from the lab to the fab stage. What’s beyond 10? Is it going to be 7, 5 or 3 next? At least for Samsung Foundry, for the next node after 10 we are in advanced pathfinding. Is it going to be FinFET? Probably too early to tell for sure. Is it going to be FinFET with another material innovation? Probably. Is it going to be Gate All Around? We are in research with a team in Albany Nanotech in New York. We can’t comment on which will be the definite path beyond that. History has taught us that innovations last at least two generations before we have to do something more radical or evolutionary.

Moroz: I actually happen to look at scaling down to 2nm node and what we see is that 7nm, if you compare nanowires — specifically vertical nanowires — they are quite a bit better for some reasons; mainly for middle of line parasitics than the lateral nanowires. If you compared 7nm nanowires with FinFETs, they are comparable in terms of overall circuit performance but at 5nm, they nanowires have distinct advantage. The more you scale, the more advantage they have. If exotic materials happen it will be a one node thing because the problem is faster materials with high mobility is that the electrons are too wide as a wave function it’s too wide. Remember why we have high-k metal gate: gate leakage mitigation. The electrons are too spread around — the wave function is too spread. If your physical dielectric thickness is less than 2nm, then the electron finds itself part of the time on the the other side of the dielectric, so it physically cannot be less than 2nm — that’s why we introduced high-k. Same thing happens with scaling: when your source is too close to the drain, the source barrier is too narrow and the particles find themselves on the drain side. So, three-five are not in the picture at 5. 7nm, maybe but is it going to be a one node thing? I’m not sure.

Low: It will be expensive.

SE: How will the industry support development for an exotic material for just one node? Is that possible?

Moroz: Economically? I didn’t model that.

Rey: It’s really quite unlikely. The perspective that we all keep in mind is that if anything radically different is going to happen either on the process side or on the design side for 7nm, we’d better know now because otherwise we’re not going to be able to actually develop it, and that is going to have an impact on what things are going to make it into production. Certainly with the most advanced 10nm companies, we’re seeing FinFETs and I would venture that it’s going to be some variation of FinFET — something that starts looking closer to Gate All Around at some point in the future but it certainly seems that with the research that has been going on there, FinFETS can still be extended beyond what we are seeing most immediately. At least that’s what the academic research seems to be indicating. The key point is that when looking into pretty much all the other technologies, they always bring some impact on either the process or the design. There are some beautiful efforts (like from Mitra and Wong) that they, from the beginning, starting saying, ‘We are going to create circuits of carbon nanotubes but we want to make sure that they are minimally disruptive from a process point of view and a design point of view.’ They were able to actually create a circuit that works. Nobody seems to be jumping in that direction because I believe it is because these interruptions are big enough that they are creating barriers for production.

Moroz: I wouldn’t bet on that horse.

Rey: For what reason?

Moroz: Too many issues; mainly, reproducibility, diameter — manufacturability basically of the nanotubes.

Low: From a current view, five years later this could be a different conversation.

SE: If it is 7nm, we have to know now, right?

Rey: Right, so we need to start looking into what’s going to happen at 5 and beyond.

Moroz: You can say it the other way around: if we don’t know by now, then it’s not going to happen.

Rey: Don’t say that but that’s the reason why this is interesting what Victor has to say about all the TCAD work that they are doing.

Moroz: This question of FinFET, nanowire, nanotube is a little bit misguided because what we see when you scale that much, what actually happens is when you scale, scale, scale, you push things closer together and your capacitance is like 1/x; capacitance is 1/dielectric thickness so when you squeeze your spacer between the gate and drain — .7x, .7x — then capacitance rises as 1/x. That’s a scary curve to ride. I think the main focus should be actually middle of line parasitics, not the channel itself — it’s much scarier, actually. We don’t see it yet, but it’s coming at 7 and 5nm.

Low: I think that’s very true. This is where we also see from a process integration, we have to go into different materials. The other challenge we see is the back end of line — with increased drive power, the back end of line is becoming a limiting factor. Electromigration issues, R&Cs not scaling fast enough to take advantage of the increased drive current from the front end. We are hoping to see more innovation. There’s Air Gap being introduced by Intel of course, but beyond Air Gap, is there something else?

SE: To that point, what are some of the other options?

Low: Short term, we are working with customers closely to help them do the necessary trade-offs in selecting metal stacks: more graded metal stacks that can help balance the R&Cs for back end of line. In the past, 28nm and above, typically SoC designs use a lot of thin metals or tight pitch metals, and then terminate with thick metals. These days what we are seeing is graded — this helps mitigate in the short term. We do have to find solutions for longer term from a back end of line materials or process innovation.

Gerousis: The design tools need to take advantage of that. If you don’t know how to deal with that metal stack, then you have an issue: you cannot take advantage of those metal stacks.

SE: So what’s happening there with the design tools?

Gerousis: Design implementation is using more metal of the upper layers, and assigning critical signals to those layers during design implementation.

SE: Does the architect or the designers working earlier in the design process need to understand those parasitics?

Gerousis: Yes, I think every SoC at 10nm and below needs to look at the entire stack, not just the device itself. You can make the device as fast as you want but the interconnect is not going to take advantage and will slow you down.

SE: How will that data be represented in the design flow?

Low: This where the engagement models with customers, as well as the EDA partners, happen even earlier. The amount of openness and transparency and information sharing has to be there. We have seen taking place where we used to throw the PDK over the wall — that can be very destructive and can hide last minute surprises. From PDK 0.9 to 1.0, everything changes. For system level definition architects like to see what’s in 0.01 PDK, then they can understand the nuances of the system itself. FinFET introduced a lot of change. Fortunately the EDA tools have matured. Double patterning introduced another set of complexity.

Rey: Absolutely, and all those models are continuously being refined. It started down from 90nm and 65nm down, having a much closer interaction between the EDA industry, the IP provider, the semiconductor fabs and they all create models to exchange this information. When you look at it today, we have to be between 1 and 2% accuracy for parasitic extraction for pretty much any value that you extract to either field solver or what is being measured. Sometimes there are issues there because in order to actually get to that accuracy, you need a very accurate representation on how the structures look like, both in materials as well as in geometries — and the semiconductor manufacturers want to protect that information because it is highly competitive. So all sorts of methods have been developed to exchange that information and be able to overcome it. That will be happening more and more.

SE: What are the formats for that?

Rey: Essentially, it is some form of encryption of information in order to be able to share that information with others that are allowed to see it.

Low: There’s a lot of concept of an IP vault — every company has a vault system so a select number of people could access the information, especially during the early days where the process IP is important, design IP is important, etc.

SE: So there is still reluctance to share certain types of information?

Low: Sure.

SE: What can be done about that? What do the EDA providers need from the foundry?

Gerousis: We look at different companies, and we see different strategies. We see some company completely closes everything in, only allows certain people – they are protected only for that foundry – cannot be used with other foundries. This is to the extreme. So you have one person for this foundry, another person for another foundry — which makes tool development not very good either because you cannot share commonalities. Physics is physics; it’s not going to be different for one foundry to the other. But people need to protect their IP.

Rey: Those issues always in the end get resolved. They don’t get resolved, we don’t have a solution.

Low: In the end, lead customers and lead projects will drive this. We try to be more proactive but many times the catalyst is still the mutual customer.

Moroz: Might this openness or closeness be a function of number of players? It used to better with a larger number of players? Now it’s going to be better with a fewer number of players?

Rey: Which players? Manufacturers?

Moroz: Foundries.

Low: The R&D guys are more open in the form of sharing technical papers or joint presentations, concepts.

Gerousis: It depends on the foundry.

Rey: So what do we have here? A general consensus that FinFETs can be stretched but then we need to jump to something, and you are absolutely convinced it’s going to vertical silicon nanowires?

Moroz: You see the issue with FinFETs is that when you scale channel length — and you have to for density — then you also have to scale the fin widths, and there are limits how thin it can go without collapsing. For that, either you make it thin and stable, which I think is physically impossible at some point; instead you make Gate All Around, which has better gate control so you can prevent channel effects and keep scaling.

Rey: Are there issues with crystallographic directions for the silicon in that case that actually create process problems?

Moroz: Not really. I think there are known preliminary technological ways to make it happen. And in terms of crystal orientation eventually we want to use the crystal orientation which is slower.

Low: With FinFET happening and tight pitch, all transistors are uni-directional, in a lateral plane. So, crystal orientation can be met, according to the design rules.

To continue reading, click here for part two.