Leti Outlines FDSOI And Monolithic 3D IC Roadmaps

Semiconductor Engineering discussed the future roadmaps for fully depleted silicon-on-insulator (FDSOI) technology and monolithic 3D chips with Maud Vinet, manager for the Innovative Devices Laboratory at CEA-Leti.

SE: What are some of the technologies being developed at the Innovative Devices Laboratory?
Vinet: The Innovative Devices Laboratory is involved with advanced CMOS. So basically, our research focus is process integration, new transistor architectures and new substrate evaluations. We also focus on 3D monolithic integration. And we are looking at new materials beyond CMOS. We also have activities in sensors integrated with CMOS.

SE: What are some of the challenges in IC scaling?
Vinet: Litho is definitely a huge challenge. Then, for the device guys, we’ve got power and energy tradeoffs to tackle. So, we try to structure our research around the materials and design. The new materials present many challenges. For example, one of the main reasons for the introduction of high-mobility materials is to boost the performance. But when they are integrated in a transistor process, are we going to preserve the intrinsic properties and are we able to get the expected gain?

SE: IBM, Leti, Soitec, ST and others are instrumental in developing FDSOI. How do you see FDSOI versus bulk finFETs?
Vinet: From my point of view, we might get different answers depending on the applications. For example, Intel went to finFETs, which from a technical point of view, is equivalent to fully-depleted SOI. From a technology point of view, finFETs are more challenging than planar FDSOI. Fully-depleted SOI is more straightforward. But depending on how much money you can spend, and depending on the market you’re addressing, you might prefer one option over another. The key is to choose the right technology for the right application.

SE: Intel went from planar to finFETs at 22nm. The foundries plan to introduce finFETs at 14nm. In contrast, the plan is to extend planar FDSOI at three nodes—28nm, 14nm and 10nm. Is that correct?
Vinet: Currently, planar FDSOI is showing that it can scale down to 10nm. There is something else unique to FDSOI, which is the versatility enabled by back-bias technology. Because of that, FDSOI is very appealing. What back bias allows you to do is tune the properties of your circuit. For example, you want part of the circuitry to be very fast. So, you could decrease your Vt to boost your performance. In another example, you can lower the Vt in order to decrease the power consumption. You can do that on small blocks. You just choose your design to take advantage of the benefits.

SE: FDSOI makes use of self-aligned contacts, right?
Vinet: Yes, and what self-aligned contacts provide is the ability to decrease the pitch. You don’t have to worry about contact misalignment.

SE: What is the main difference between the three planar FDSOI versions at 28nm, 14nm and 10nm?
Vinet: 28nm FDSOI is unstrained silicon technology. Moving to 14nm, we go to a strained-silicon technology. The strain is in the PFET with the addition of silicon germanium. So it features a SiGe channel for PFET and in-situ doped RSD to leverage the performance by 40% with respect to 28nm FDSOI. Leti, ST and IBM have been working together to bring up 14nm FDSOI with 11 metal layers at a 64nm pitch.

SE: On your roadmap, the PDKs for 14nm FDSOI were due out in the third quarter of 2013. The PDKs for 10nm are slated a year later. What will 10nm FDSOI technology look like?
Vinet: Moving further away to 10nm, it’s going to be a dual-strain technology. NFET and PFET are going to be strained. Compared to 14nm, PFET will be even more strained using a higher germanium content in the strain itself. We could see higher germanium content in the channel if needed. Currently, we are benchmarking all of the options.

SE: What happens to the NFET for 10nm FDSOI?
Vinet: We are adding more strain. The way to do that is to use sSOI or strained-SOI. We have demonstrated that sSOI is very effective to boost NFET performance by 20%.

SE: The industry is talking about moving to high-mobility III-V materials at 7nm and beyond. Any thoughts?
Vinet: Indium-gallium-arsenide may be used in the NFET side, with a high germanium content on PFET. People are more or less in agreement with this scheme. But it is very challenging to integrate III-V. This is a question of cost. In research, we are benchmarking the various options.

SE: On the roadmap, the plan is to go to SOI-based finFETs at 7nm and 5nm, right?
Vinet: I can’t comment on that. I would prefer to let IBM comment and provide the latest developments. IBM is leading the way on the research on this topic. But basically, SOI finFET has advantages with respect to bulk finFETs, because of the dielectric isolation of the source-drain.

SE: Why not extend planar FDSOI to 7nm?
Vinet: When you go to 7nm, the challenge is to preserve the electrostatics. The electrostatics are determined by the ratio of the gate length over the silicon thickness. If you decrease the gate length, you have to decrease the silicon thickness. And currently, we can agree that we can go down to 3.5nm to 4nm in terms of silicon thickness. But going down would be too challenging from a technology point of view.

SE: Besides FDSOI, Leti is also developing monolithic 3D technology. What is that about?
Vinet: You have one layer of transistors. Then, you stack another layer of transistors on top. This is done using a blanket wafer. This allows you to have lithographic alignment precision between the two layers. So, you have a connection at the transistor level. Instead of TSVs, the connections are like contacts. So, you have state-of-the-art transistors on top of state-of-the-art transistors. You would also have state-of-the-art contacts. On the other hand, you could have other options. One option is to have 14nm on the bottom layer and 65nm on top. You don’t need to be state-of-the-art. There is a lot of versatility.

SE: How is this done?
Vinet: We start by processing the bottom transistor. And in a monolithic way, we process the top transistor. We can align the transistor on top of each other in a lithographic alignment. And then, when we want to connect them, we have a huge number of interconnections between the two layers. In terms of alignment performance, we are within a few tenths of a nanometer.

SE: When is the insertion point for this technology?
Vinet: Currently, we are trying to be ready for 14nm or 10nm. But on the other hand, this could be at the end of the roadmap technology, when people can’t scale anymore in 2D.

SE: What is the status of this program within Leti?
Vinet: Currently, we are developing the building blocks and the technology enablers. We are working with the designers to identify the best-suited applications for this technology. Since the beginning, we have been in close collaboration with the designers. We are just starting to identify the applications.

SE: What are the main challenges?
Vinet: The main challenge is to process the top layer. When you process the top layer, you don’t want to destroy the bottom one.

SE: What are the advantages of monolithic 3D versus 3D TSV technology?
Vinet: I wouldn’t say it’s better in general, but monolithic 3D offers more versatility. You could have more connections between your two layers. And basically, the distance between the two contacts can be as short as 16nm.

SE: Who else is developing this technology?
Vinet: Currently, we are the leaders. We have almost seven years of experience with this technology. We are not working on it by ourselves. We have a couple of customers and industrial partners working on the technology with us. You’ve also got a lot of interest from the fabless companies.

SE: Finally, your lab is also working on sensor technology, right?
Vinet: This is an activity where we take advantage of nanowires as sensors. There is a startup that was created last year by Leti and the California Institute of Technology. The company is called Apix. Apix is developing a nano-sensor gas chromatography system.