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Manufacturing Bits: June 16

GaN power modules; Fan-out with GaN.

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GaN power modules
Gallium-nitride (GaN) devices are emerging in several markets, such as power semiconductors and RF.

GaN, a binary III-V compound, is a wide-bandgap technology, meaning it is faster and more efficient than silicon-based devices. GaN has 10 times the breakdown field strength with double the electron mobility than silicon.

Generally, some GaN vendors don’t use a traditional IC package. The issue is that a package is prone to reliability problems in GaN. Instead, vendors take bare dies, hermetically seal the devices and place them on a board.

For GaN, the industry is developing new and traditional packaging types. At the recent IEEE Electronic Components and Technology Conference (ECTC), for example, Leti described a new power module based on ceramic substrates for GaN devices.

The module consists of two ceramic substrates, which face each other and encapsulate the components. The components include bare GaN transistor dies.

In this module, Leti developed a 650V double-side cooling inverter using ceramic substrates. It exhibits a parasitic inductance of 3nH at 100MHz, according to Leti.

“Wideband gap (WBG) semiconductors are pushing the power module architectures towards a new paradigm in order to reduce the parasitic elements (inductive and capacitive) and improve the thermal management,” said Christine Laurant from Leti, in a paper at ECTC. (Others contributed to the work.) “Indeed, the switching operations are faster than with silicon devices; therefore, interconnection parasitic elements become a major limitation, which prevents the designer from getting the best out of the WBG transistors. In order to reduce the parasitic inductances and for the sake of size reduction, the power density is increased, at the expense of a possible loss density, requiring a better performing thermal management of the power module.”

Leti’s work was carried out and tested with dies having a low current capability. “The 3D architecture presented in this work allows achieving low parasitic inductance (3,3nH) and a good symmetry of the parasitic capacitances (EMI mitigation),” Laurant said. “The inductance could be reduced further by decreasing the distance between the substrates. This distance is limited by the capacitor and transistor die thicknesses, although the die could be grinded further and another thinner capacitor technology like the silicon one could be used. The phase to ground capacitance (83pF) could be easily decreased by reducing the phase plane area (antiparallel diode suppression) or the substrate backside area on the opposite surface.”

Fan-out with GaN
At ECTC, Fraunhofer described a fan-out technology for RF GaN applications. In this work, the R&D organization integrated a GaN-based power amplifier in a fan-out package.

In RF GaN, the package is usually based on a ceramic housing with air cavities and metal flanges. Some assemble RF GaN in leadframe packages.

“Driven by 5G or radar applications there is an increasing market for GaN device for RF power applications,” said Tanja Braun, group manager at Fraunhofer. “GaN component packaging is done today mainly by wire bonding in combination with expensive ceramic based packaging solutions. Cost efficient fan-out wafer-level packaging (FOWLP) is considered a promising solution for GaN devices, offering short and low inductance interconnects, high miniaturization, good thermal solutions, potential lower cost and the possibility of integrating passive components and structure in the package and redistribution layer.”

Fan-out with GaN is challenging. GaN devices are thin. They have fragile air bridge structures on the active die side. There are other issues as well.

Fraunhofer’s paper describes the technology development of a GaN-based power amplifier in fan-out. “For the GaN backside access, two different approaches have been evaluated. First, the attachment of a Cu heatsink on the GaN backside before molding is followed by a backgrinding step into the Cu heatsink. Second, the drilling of vias through the mold to the GaN backside is followed by direct metallization of the vias for thermal and possible electrical connection,” Braun said.

“The thermal release tape used has been carefully selected and the process steps, such as pick-and-place assembly, compression molding and debonding, have been optimized to avoid any damage of GaN die and air bridges. Influences of the packaging materials on the RF performance of the die have also been tested. Finally the different technology blocks developed have been combined to build a GaN-based power amplifier in FOWLP,” Braun added.



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