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Manufacturing Bits: Oct. 26

GaN finFETs; scaling GaN; FeFETs; 1nm power rails.

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GaN finFETs, scaling GaN
At the upcoming IEEE International Electron Devices Meeting (IEDM) in San Francisco, a slew of entities will present papers on the latest technologies in R&D. The event, to be held Dec. 11–15, involve papers on advanced packaging, CMOS image sensors, interconnects, transistors, power devices and other technologies.

At IEDM, Intel will present a paper on a GaN-on-silicon finFET technology. Combining CMOS with gallium nitride (GaN) could enable a new class of heterogeneous devices. “If GaN technology could be integrated effectively with CMOS technology and built using mainstream silicon CMOS tools and fabrication processes, then high-performance, energy-efficient and low-cost solutions could be created for next-generation PC/mobile devices, data centers, automotive radar, communication networks and other applications,” according to an abstract from Intel.

(To find abstract, click here. Look for Paper 11.1: “Advanced Scaling of Enhancement-Mode High-K Gallium Nitride-on-300mm-Si(111) Transistor and 3D Layer Transfer GaN-Silicon FinFET CMOS Integration. Click “Paper 11.1 with caption.”)

GaN and other technologies are used in power electronics. Using solid-state devices, power electronics control and convert electrical power in systems. These include cars, cellphones, power supplies, solar inverters, trains and wind turbines. Power semiconductors are specialized transistors that boost the efficiencies and minimize the energy losses in systems. Power semis operate like a switch in systems, allowing the electricity to flow in the “on” state and stop it in the “off” state.

GaN, a binary III-V material, is used for LEDs, power semis and RF devices. GaN-based power semis are used in automotive, data centers, military-aerospace and other apps. GaN power semis range from 15 to 900 volts. GaN has a 3.4 electronvolt bandgap, which is higher than SiC. GaN has a breakdown field that is ten times higher than silicon. The electron mobility for GaN is double as compared to silicon.

GaN power semis are lateral devices. A source, drain and gate are formed on the structure. Meanwhile, finFETs are advanced transistors used in a wide range of chips.

Intel proposes to combine the two technologies. To this end, Intel researchers will describe an enhancement-mode GaN-on-Si NMOS finFET, which is integrated with PMOS finFET technology. All of this is built on a 300mm substrate.

Researchers have demonstrated a low-loss inverter based on the technology. The inverter consists of a bottom GaN E-mode high-k NMOS finFET transistor and a top PMOS finFET transistor. The NMOS GaN finFET features the narrowest GaN fin to date (width=25nm) and a short gate length (30nm), according to Intel. It is integrated with a PMOS finFET having a 35nm fin width.

Then, in a separate paper at IEDM, Virginia Polytechnic Institute, the University of Southern California, Cambridge University, Enkris Semiconductors and Qorvo will present a paper that will describe a new GaN power device.

The device, called a Multi-Channel Monolithic-Cascode high-electron-mobility transistor (MC2-HEMT), operates at a 10kV breakdown voltage and has a specific on-resistance ~2.5x smaller than silicon carbide (SiC). “Made from AlGaN/GaN, the device monolithically integrates a low-voltage, enhancement-mode HEMT based on a single two-dimensional electron-gas (2DEG) channel, with a high-voltage, depletion-mode HEMT based on a stacked 2DEG multi-channel,” according to the abstract.

(To find abstract, click here. Look for Paper 5.5: Multi-Channel Monolithic-Cascode HEMT (MC2-HEMT): A New GaN Power Switch up to 10 kV. Click Paper 5.5 with caption)

FeFETs
The semiconductor industry continues to work on new memory types, including the so-called ferroelectric FETs (FeFETs).

Still in R&D, a FeFET makes use of an existing logic transistor with a high-k/metal-gate stack based on hafnium oxide. The gate insulator is then modified with ferroelectric properties. FeFETs are sometimes called ferroelectric RAM (FeRAM).

At IEDM, Intel will describe how they built FeRAM with deep-trench capacitors that showed good performance (read/write speed of ~2ns) and reliability (endurance >1012 cycles), with high levels of uniformity at the 300mm wafer scale.

(To find abstract, click here. Look for Paper 33.2: “FeRAM using Anti-ferroelectric Capacitors for High-speed and High-density Embedded Memory” Click Paper 33.2 with caption.)

FeFETs are promising for both standalone and embedded applications. “However, there isn’t yet an atomic-level understanding of the relationship between a given surface functionalization and ferroelectric performance; most attempts to engineer FE performance by altering a hafnium film’s surface characteristics have been laborious trial-and-error efforts,” according to Samsung.

At IEDM, Samsung will describe the development of an automated algorithm for searching thermodynamically stable geometries of surface-functionalized ferroelectric hafnium oxide.

Researchers at Samsung used it to systematically investigate the surface functionalities of eight different hafnium crystal orientations, and how they impacted performance. The technique is extendable to other oxide surfaces and functional groups, and will lead to precise control of hafnium’s ferroelectric properties for use in future devices, according to the abstract.

(To find abstract, click here. Look for Paper 15.1: “Surface-Functionalized Hafnia with Bespoke Ferroelectric Properties for Memory and Logic Applications.” Click Paper 15.1 with caption.)

1nm rails
In today’s transistors, the big bottleneck are the copper interconnects. At advanced nodes, the copper interconnects create unwanted resistance and capacitance in devices.

“One possible way to continue scaling is to reconfigure the interconnect so that it takes up less space. In current designs, the top interconnect layer is what routes power to a chips’ transistors,” according to an abstract from Imec and ASM International. “If this ‘power rail’ could be built closer to them – in the substrate right beneath them – then the interconnect stack could be reduced in height, the number of interconnections could be reduced, and smaller chip architectures would result.”

But it isn’t clear which metals a buried power rail (BPR) should be made from in order to address electrical performance, and for manufacturability.

At IEDM, Imec and ASM International will discuss their experiments evaluating different metals both for the BPR itself and also for the low-resistance contacts needed between the BPR and the through-silicon-vias that run through a chip’s different layers. “For future 3nm transistors, a tungsten BPR optimizes line and contact resistance, and for 1nm and 2nm devices, molybdenum (Mo) appears better for the BPR and ruthenium (Ru) for the via contacts,” according to the abstract.

(To find abstract, click here. Look for Paper 22.5: “Buried Power Rail Metal Exploration Towards the 1nm Node. Click Paper 22.5 with caption.)



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