New Reliability Issues

By Arvind Shanmugavel
Reliability of ICs is a topic of growing concern with every technology node migration. With the onset of the 20nm process node from different foundries, reliability verification has taken center stage in design kits—and for good reason. Reliability margins have continued to decrease and have reached an inflection point at the 20nm node. The design and EDA communities have been re-tooling in order to meet the tight design rule requirements from the foundries.

IC reliability simulations are typically classified into three categories: electromigration (EM), electrostatic discharge (ESD), and thermal analysis. Accounting for these reliability concerns during the design process and verifying them with the appropriate simulations has become mandatory for the 20nm process node.

Any type of reliability verification on the Power Delivery Network (PDN) or the Signal Network for an IC requires the design to be extracted for resistance and capacitance parasitics. Extraction of metal geometries in the smaller process technologies heavily depends on the width of the metal and the spacing to the neighboring metals. This phenomenon is called wire biasing and must be considered during the extraction step for reliability verification.

Double pattering is an approach used by foundries to improve the minimum geometries between laid-out wires on a chip. Extraction tools need to understand the effect of double and triple patterning when performing parasitic extraction. Dielectric thickness biasing is another phenomenon to be considered when extracting capacitance. With capacitance being a strong function of dielectric thickness, it is imperative to regard these effects during extraction.

Technology scaling usually has an adverse effect on EM. As metal stack geometries become smaller, the variability in actual manufacturing is becoming larger. This variability in metal geometry, along with lowered EM limits, has imposed strict rules on EM checks during the design signoff process. Designers no longer have the latitude to design with a ‘correct by construction’ approach to account for tight EM limits. The foundries are paying attention to certain EM checks based on the topology of the metal and vias. EM rules no longer have a simple current density limit for a given width of metal. Complex polynomial rules that are dependent on the width, length and temperature of the metal are common. Current direction-aware EM limits provided by foundries give proper consideration to vias with different current directions.

The accuracy of currents calculated during an EM analysis is important for reliability sign-off. In general, using an average current consumed by instances is enough for an accurate power EM analysis. However, for smaller power/ground networks that are part of an IP or an analog domain, a transient simulation needs to be performed to capture the accurate switching behavior of the currents. The currents captured from these simulations must be used for power EM analysis to calculate the average, root mean square (RMS) and peak EM violations. For Signal EM analysis, the accuracy of the root mean square (RMS) current is critical for digital place and route nets. With tight EM limits for narrow signal nets, the accuracy of current plays a very important role in the accuracy of the EM violation.

Thermal impact on EM is another aspect of reliability verification that has plagued the design community for more than a decade. Since temperature has an inverse exponential relationship to the current limit, it is important to check the EM limit at an accurate operating temperature of the die. Signing-off with a pessimistic temperature can result in several false EM violations, leading to over-design. With narrowing EM margins at the 20nm node, temperature is yet another aspect that needs to be accurately modeled for die-level reliability verification.

Reliability platforms that can accurately model and simulate the currents in every net, decipher advanced EM rules and apply thermal corrections to simulations are mandatory for 20nm designs. Platforms such as RedHawk and Totem from Apache provide the ability to analyze complex IP and SoCs with full-chip capacity and silicon-correlated accuracy, and have been certified for TSMC’s 20nm process.

The 20nm node has seen major changes in process manufacturing to meet low-power and high-speed design needs. The radical changes to metal stack, EM rules, ESD guidelines and thermal requirements at 20nm have forced the EDA community to quickly respond to these challenges. Design teams are not only re-tooling their flows, but are also adopting newer sign-off methodologies for advanced reliability.

—Arvind Shanmugavel is director of application engineering at Apache Design Inc.