Research Bits: July 1

Copper-to-copper bonding for GaN integration

Researchers from MIT, Georgia Tech, and Air Force Research Laboratory propose a bonding process to integrate gallium nitride (GaN) transistors onto standard silicon CMOS chips. They used the process to create a power amplifier.

“We wanted to combine the functionality of GaN with the power of digital chips made of silicon, but without having to compromise on either cost of bandwidth. We achieved that by adding super-tiny discrete gallium nitride transistors right on top of the silicon chip,” said Pradyot Yadav, an MIT graduate student, in a statement.

The process involves fabricating numerous transistors on the surface of a GaN wafer, which is then diced into individual transistors measuring 240 by 410 microns. Each transistor has a copper pillar on top, which is then bonded directly to copper pillars on the CMOS chip.

The team said that power amplifiers fabricated using the approach achieved higher bandwidth and better gain than devices made with traditional silicon transistors. [1]

Simple 2D computer

Researchers from Pennsylvania State University, Indian Institute of Technology, and Jadavpur University used two different 2D materials to build a one instruction set CMOS computer capable of simple logic operations.

The team grew large sheets of molybdenum disulfide, which was used for n-type transistors, and tungsten diselenide, which was used for p-type transistors, using metal-organic chemical vapor deposition (MOCVD). They were able to adjust the threshold voltages of both n- and p-type transistors by tuning the device fabrication and post-processing steps.

“Our 2D CMOS computer operates at low-supply voltages with minimal power consumption and can perform simple logic operations at frequencies up to 25 kilohertz,” said Subir Ghosh, a doctoral student in engineering science and mechanics at Penn State, in a press release. “We also developed a computational model, calibrated using experimental data and incorporating variations between devices, to project the performance of our 2D CMOS computer and benchmark it against state-of-the-art silicon technology. Although there remains scope for further optimization, this work marks a significant milestone in harnessing 2D materials to advance the field of electronics.” [2]

Stacking processors and memory

Researchers from the Institute of Science Tokyo presented several enabling technologies for a 3D stacked computing architecture that places processing units directly above DRAM.

The integration approach, which the team calls BBCube, uses a face-down chip-on-wafer process. Inkjet technology and selective adhesive coating were used to perform sequential bonding of different chip sizes onto a 300 mm waffle wafer with a narrow chip-to-chip spacing of 10 μm and a minimal mount loading time of less than 10 milliseconds. To ensure a strong bond, the team developed a heat-resistant adhesive material with an organic-inorganic hybrid structure.

To improve power delivery, capacitors were embedded between the processor and DRAM, redistribution layers were implemented on the waffle wafer, and though-silicon vias were placed in wafer lanes and DRAM scribe lines.

“These innovations reduced the energy required for data transmission to one-fifth to one-twentieth of that in conventional systems, while also suppressing power supply noise to below 50 mV,” said Norio Chujo, a processor from the Institute of Integrated Research’s WOW Alliance Heterogeneous and Functional Integration Unit at Institute of Science Tokyo, in a release. [3]

References

[1] P. Yadav, J. Wang, D. A. Baig, et al. 3D-Millimeter Wave Integrated Circuit (3D-mmWIC): A Gold-Free 3D-Integration Platform for Scaled RF GaN-on-Si Dielets with Intel 16 Si CMOS. IEEE Radio Frequency Integrated Circuits Symposium. https://rfic-ieee.org/technical-program/rfic-technical-sessions?date=2025-06-17

[2] Ghosh, S., Zheng, Y., Rafiq, M. et al. A complementary two-dimensional material-based one instruction set computer. Nature 642, 327–335 (2025). https://doi.org/10.1038/s41586-025-08963-7

[3] Y. Satake, W. Doi, H. Kato, et al. “Face-Down Bonding and Heterogeneous Chiplet Integration by Using Bumpless Chip-on-Wafer (COW) with Waffle Wafer Technology.” N. Araki, T. Fukuda, T. Ohba. “Advanced Resin Material Enabling Room-Temperature Bonding for WOW and COW 3DI Applications.” N. Chujo, H. Ryoson, K. Sakui, et al. “BBCube 3D: Fully Vertical Heterogeneous Integration of DRAMs and xPUs Using a New Power Distribution Highway.” Proceedings of the 2025 IEEE 75th Electronic Components and Technology Conference (ECTC)