A technical paper titled “A cross-process Spectre attack via cache on RISC-V processor with trusted execution environment” was published by researchers at University of Electro-Communication, Academy of Cryptography Techniques, Technology Research Association of Secure IoT Edge Application based on RISC-V Open Architecture (TRASIO), and AIST.
“This work proposed a cross-process exploitation scheme for conducting the cache side-channel attack, Spectre, on RISC-V processors with a trust execution environment. Practical experiments are provided to verify the protected enclave’s security on RISC-V processors with the TEE,” states the paper.
Find the technical paper here. Published December 2022.
Le, Anh-Tien, et al. “A cross-process Spectre attack via cache on RISC-V processor with trusted execution environment.” Computers and Electrical Engineering 105 (2023): 108546.
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