tag: 16nm

More Problems Ahead
By Ed Sperling - 14 Aug, 2014 - Comments: 3

Semiconductor Engineering sat down to discuss future scaling problems with Lars Liebmann, a fellow at IBM; Adam Brand, managing director of transistor technology at Applied Materials; Karim Arabi, vice president of engineering at Qualcomm; and Srinivas Banna, a fellow for advanced technology architecture at GlobalFoundries. SE: We’re starting to hear talk about octuple patterning. We’ve ... » read more

What’s Next For Memory?
By Mark LaPedus - 14 Aug, 2014 - Comments: 4

Apple, Samsung and others are developing the next wave of smartphones and tablets. OEMs want to integrate new memory schemes that provide more bandwidth at lower power. But there are some challenges in the arena that are prompting memory makers to rethink their mobile DRAM roadmaps. The conventional wisdom was that memory makers would ship mobile DRAMs based on the new LPDDR4 interface stand... » read more

Why The Next Couple Process Nodes Are So Critical
By Ed Sperling - 14 Aug, 2014 - Comments: 0

In the greater scheme of things, one process node doesn't matter all that much. In fact, it has become common practice for big chipmakers to skip nodes for some of their chips as power issues becoming increasingly complex, time-to-market windows shrink and leapfrogging is viewed as a way to maximize resources while remaining über-competitive. But the next process node, and certainly the nex... » read more

Pattern Matching: Blueprints For Further Success
By Mentor, a Siemens Business - 14 Aug, 2014 - Comments: 0

Design patterns have a wide variety of applications in the design, verification and test flows of IC development. From significantly reducing rule deck complexity to simplifying the task of avoiding known yield detractors to enhancing workflows such as design rule waiver recognition, pattern matching has become a useful tool throughout design, verification, and test process. Learn how Calibre P... » read more

Who’s Winning The FinFET Foundry Race?
By Mark LaPedus - 14 Aug, 2014 - Comments: 5

The leading-edge foundry business is challenging. For starters, foundry vendors require vast resources, gigantic fabs and lots of know-how. And yet, it’s still difficult to make money in this business. That has certainly proven to be the case in the planar transistor era, but the challenges and costs are escalating as foundry vendors begin to ramp up finFET technologies at the 16nm/14nm no... » read more

Executive Insight: Taher Madraswala
By Ed Sperling - 11 Aug, 2014 - Comments: 1

Semiconductor Engineering sat down with Taher Madraswala, president of Open-Silicon, to talk about future challenges, opportunities and changes. What follows are excerpts of that interview. SE: What worries you most? Madraswala: What worries me at the industry-level is the growing effect that business constraints are having on product innovation. We’ve done a very good job of advancing ... » read more

Improving 2.5D Components
By Ed Sperling - 07 Aug, 2014 - Comments: 1

A lot of attention is being focused on improving designs at established, well-tested nodes where processes are mature, yields are high, and costs are under control. So what does this mean to stacking die? For 2.5D architectures, plenty. For 3D, probably not much. Here’s why: The advantage of 2.5D is that it can utilize dies created at whatever node makes sense. While the initial discuss... » read more

Power Reduction Techniques
By Mary Ann White - 07 Aug, 2014 - Comments: 0

As 16nm and 14nm finFET process nodes come into production toward the end of this year, the performance (up to 30% vs. 28nm planar CMOS), power (~30%) and area (up to ~50%) benefits have been well documented. The same can be said for the 28nm FD-SOI process as it gains more traction in the marketplace touting similar performance and power improvements as those for FinFET when compared against i... » read more

Changing The Meaning Of Sign-Off
By Muhammad Zakir - 07 Aug, 2014 - Comments: 0

Chip development teams are faced with an ever-increasing number of power integrity and reliability challenges these days, especially as designs adopt FinFET technology. Even those with the most thorough sign-off checks often encounter unexpected surprises that quickly turn into tape-out hurdles, or worse yet, extensive re-design. The best way to avoid this scenario and ensure a smoother sign-of... » read more

Supporting LP In New Process Nodes
By Ann Mutschler - 10 Jul, 2014 - Comments: 0

Manufacturing process nodes and EDA tools are advancing all the time, but not always utilized at the same pace. And from a tools perspective, there are challenges to supporting low power in new process nodes while maintaining and improving the existing process nodes. One way design teams address this is by leveraging the most advanced software on the less-than-bleeding edge designs. To th... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2024 SMG   |  Terms of Service  |  Privacy Policy