Next-Gen Transistors

By Ed Sperling - 07 Mar, 2022 - Comments: 0

Nanosheets, or more generally, gate-all-around FETs, mark the next big shift in transistor structures at the most advanced nodes. David Fried, vice president of computational products at Lam Research, talks with Semiconductor Engineering about the advantages of using these new transistor types, along with myriad challenges at future nodes, particularly in the area of metrology. » read more

Transistors Reach Tipping Point At 3nm

By Mark LaPedus - 23 Feb, 2022 - Comments: 1

The semiconductor industry is making its first major change in a new transistor type in more than a decade, moving toward a next-generation structure called gate-all-around (GAA) FETs. Although GAA transistors have yet to ship, many industry experts are wondering how long this technology will deliver — and what new architecture will take over from there. Barring major delays, today’s GAA... » read more

High-NA EUVL: the next major step in lithography

By Technical Paper Link - 05 Oct, 2021 - Comments: 0

"In the course of 2025, we expect to see the introduction of the first high-NA extreme ultraviolet (EUV) lithography equipment in high-volume manufacturing environments. These next-generation lithography systems will be key to advance Moore’s Law towards the logic 2nm technology generation and beyond. In this article, imec scientists and engineers involved in preparing this major engine... » read more

Manufacturing Bits: March 8

By Mark LaPedus - 08 Mar, 2021 - Comments: 0

Two-beam EUV lithography At the recent SPIE Advanced Lithography conference, Nikon gave a presentation on a two-beam extreme ultraviolet (EUV) lithography technology. Still in the conceptual phase, Nikon’s so-called EUV Projection Optical Wafer Exposure Ruling Machine, or EUV Power Machine, is designed for the 1nm node or so. The proposed system has a minimum resolution of 10nm for lines ... » read more

Predicting Reliability At 3/2nm And Beyond

By Ed Sperling - 08 Dec, 2020 - Comments: 0

The chip industry is determined to manufacture semiconductors at 3/2nm — and maybe even beyond — but it's unlikely those chips will be the complex all-in-one SoCs that have defined advanced electronics over the past decade or so. Instead, they likely will be one of many tiles in a system that define different functions, the most important of which are highly specialized for a particular app... » read more

EUV Challenges And Unknowns At 3nm and Below

By Mark LaPedus - 19 Nov, 2020 - Comments: 1

The chip industry is preparing for the next phase of extreme ultraviolet (EUV) lithography at 3nm and beyond, but the challenges and unknowns continue to pile up. In R&D, vendors are working on an assortment of new EUV technologies, such as scanners, resists, and masks. These will be necessary to reach future process nodes, but they are more complex and expensive than the current EUV pro... » read more

A Node Too Far?

By Ed Sperling - 23 Apr, 2020 - Comments: 1

Physics is an unforgiving master. While the semiconductor industry has been actively developing new transistor structures, new materials for interconnects and lining trenches, and new approaches to alleviate congestion at the lowest metal levels, it also has been playing an accelerating game of Whac-a-Mole. Whenever a problem pops up, the solution to that problem is never complete and more prob... » read more

Making Chips At 3nm And Beyond

By Mark LaPedus and Ed Sperling - 16 Apr, 2020 - Comments: 4

Select foundries are beginning to ramp up their new 5nm processes with 3nm in R&D. The big question is what comes after that. Work is well underway for the 2nm node and beyond, but there are numerous challenges as well as some uncertainty on the horizon. There already are signs that the foundries have pushed out their 3nm production schedules by a few months due to various technical issu... » read more

Controlling Variability And Cost At 3nm And Beyond

By Ed Sperling - 22 May, 2019 - Comments: 1

Richard Gottscho, executive vice president and CTO of Lam Research, sat down with Semiconductor Engineering to talk about how to utilize more data from sensors in manufacturing equipment, the migration to new process nodes, and advancements in ALE and materials that could have a big impact on controlling costs. What follows are excerpts of that conversation. SE: As more sensors are added int... » read more

Transistor Options Beyond 3nm

By Mark LaPedus - 15 Feb, 2018 - Comments: 18

Despite a slowdown in chip scaling amid soaring costs, the industry continues to search for a new transistor type 5 to 10 years out—particularly for the 2nm and 1nm nodes. Specifically, the industry is pinpointing and narrowing down the transistor options for the next major nodes after 3nm. Those two nodes, called 2.5nm and 1.5nm, are slated to appear in 2027 and 2030, respectively, accord... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?